ORSPI4 datasheet(202/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

202

ORSPI4 SERDES External I/O Description

This section describes device I/O signals to/from the SERDES. Table 83 lists the external signals that interface to

the SERDES block.

Table 83. SERDES External Interface Signals

Pin Name

Direction

O = FPSC Output

I = FPSC Input

Description

SERDES Interface Pins

HDINP_A

Serial Input for channel A

HDINN_A

HDINP_B

Serial Input for channel B

HDINN_B

HDINP_C

Serial Input for channel C

HDINN_C

HDINP_D

Serial Input for channel D

HDINN_D

HDOUTP_A

Serial Output for channel A

HDOUTN_A

HDOUTP_B

Serial Output for channel B

HDOUTN_B

HDOUTP_C

Serial Output for channel C

HDOUTN_C

HDOUTP_D

Serial Output for channel D

HDOUTN_D

REFCLKP

Reference clock to SERDES quad

REFCLKN

REXT

Reference resistor

REXTN

Reference resistor. A 3.32 KW ± 1% resistor must be connected

across REXT and REXTN. This current should handle a total of

300

μA.

Misc System Signals

RESETN

Global Reset

Integrated 50K pull-down allows chip to stay in reset state when

external driver loses power

TESTMD[1:0]N

LVTTL test mode pins with integrated 50K pull-ups that default

chip into operational mode when un-driven.

PDN

Power-down active low. Puts Core into low-power (non-func-

tional) state.

TRISTN

Active low control input causes all output pins to be disabled.

(See Note 1)

TESTCLK

Chip test pin. Integrated 50K pull-up

1. Should be externally connected on board to 3.3 V pullup resistor.

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