ORSPI4 datasheet(198/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

198

TDI, TCK, TMS

If boundary-scan is used, these pins are test data in, test clock, and test mode select inputs. If

boundary-scan is not selected, all boundary-scan functions are inhibited once conﬁguration is

complete. Even if boundary-scan is not used, either TCK or TMS must be held at logic 1 during

conﬁguration. Each pin has a pull-up enabled during conﬁguration.

I/O After conﬁguration, these pins are user-programmable I/O if boundary scan is not used.

RDY/BUSY/RCLK

During conﬁguration in asynchronous peripheral mode, RDY/RCLK indicates another byte can

be written to the FPGA. If a read operation is done when the device is selected, the same sta-

tus is also available on D7 in asynchronous peripheral mode.

During the master parallel conﬁguration mode, RCLK is a read output signal to an external

memory. This output is not normally used.

I/O After conﬁguration this pin is a user-programmable I/O pin.

HDC

High During Conﬁguration is output high until conﬁguration is complete. It is used as a control

output, indicating that conﬁguration is not complete.

I/O After conﬁguration, this pin is a user-programmable I/O pin.

LDC

Low During Conﬁguration

is output low until conﬁguration is complete. It is used as a control out-

put, indicating that conﬁguration is not complete.

I/O After conﬁguration, this pin is a user-programmable I/O pin.

INIT

I/O INIT is a bidirectional signal before and during conﬁguration. During conﬁguration, a pull-up is

enabled, but an external pull-up resistor is recommended. As an active-low open-drain output,

INIT

is held low during power stabilization and internal clearing of memory. As an active-low

input, INIT holds the FPGA in the wait-state before the start of conﬁguration.

After conﬁguration, this pin is a user-programmable I/O pin.

CS0, CS1

CS0

and CS1 are used in the asynchronous peripheral, slave parallel, and microprocessor con-

ﬁguration modes. The FPGA is selected when CS0 is low and CS1 is high. During conﬁgura-

tion, a pull-up is enabled.

I/O After conﬁguration, if MPI is not used, these pins are user-programmable I/O pins.

RD/MPI_STRB

is used in the asynchronous peripheral conﬁguration mode. A low on RD changes D[7:3]

into a status output. WR and RD should not be used simultaneously. If they are, the write strobe

overrides.

This pin is also used as the

MPI data transfer strobe. As a status indication, a high indicates

ready, and a low indicates busy.

WR/MPI_RW

WR is used in asynchronous peripheral mode. A low on WR transfers data on D[7:0] to the

FPGA.

In MPI mode, a high on MPI_RW allows a read from the data bus, while a low causes a write

transfer to the FPGA.

I/O After conﬁguration, if the MPI is not used, WR/MPI_RW is a user-programmable I/O pin.

PPC_A[14:31]

During MPI mode the PPC_A[14:31] are used as the address bus driven by the PowerPC bus

master utilizing the least-signiﬁcant bits of the PowerPC 32-bit address.

MPI_BURST

MPI_BURST is driven low to indicate a burst transfer is in progress in MPI mode. Driven high

indicates that the current transfer is not a burst.

MPI_BDIP

MPI_BDIP is driven by the PowerPC processor in MPI mode. Assertion of this pin indicates that

the second beat in front of the current one is requested by the master. Negated before the burst

transfer ends to abort the burst data phase.

MPI_TSZ[0:1]

MPI_TSZ[0:1] signals are driven by the bus master in MPI mode to indicate the data transfer

size for the transaction. Set 01 for byte, 10 for half-word, and 00 for word.

A[21:0]

During master parallel mode A[21:0] address the conﬁguration EPROMs up to 4M bytes.

I/O If not used for MPI these pins are user-programmable I/O pins after conﬁguration.

MPI_ACK

MPI mode this is driven low indicating the MPI received the data on the write cycle or

returned data on a read cycle.

I/O If not used for MPI these pins are user-programmable I/O pins after conﬁguration.

Table 79. Pin Descriptions (Continued)

Symbol

I/O

Description

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