ORSPI4 datasheet(194/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

194

Recommended Power Supply Connections

Ideally, a board should have the power supplies described below:

• VDD33, VDD33_FPGAPLL and VDDIO supplies for the FPGA Logic

• A single 1.5 V source to supply power to FPGA and core digital logic. (VDD15)

• A dedicated 1.5 V power supply for the SERDES analog power pins. This will allow the end user to minimize

noise. The guard band pins can also be sourced from the analog power supplies. (VDD_ANA, VDDGB)

• SERDES TX output buffer power. The power supplies to the SERDES TX output buffers should be isolated from

the rest of the board power supplies. Special care must be taken to minimize noise when providing board level

power to these output buffers. The power supply can be 1.5 V or 1.8 V depending on the end application.

(VDDOB)

• SERDES RX input buffer power. The power supplies to the SERDES RX input buffers should be isolated from the

rest of the board power supplies. Special care must be taken to minimize noise when providing board level power

to these input buffers. The power supply can be 1.5 V or 1.8 V depending on the end application. (VDDIB)

• An isolated 1.5V supply for the VDDA_SPI to minimize noise from the common 1.5V board supply.

(VDD_SPI[A:D])

• The memory controller bus requires a dedicated 1.5V supply connected to the VDDH pins for HSTL output buffer

supply voltage. (VDDH)

• The HSTL input buffers of the Memory Controller require a voltage reference connected to the REFI pins which

is half the VDDH supply. This supply should be ﬁltered, and should not exceed a peak-to-peak AC noise of 2% of

the VREF (DC). The HSTL buffer scheme also requires a termination resistor per signal. It is recommended that

the clock pin termination be ﬁltered separately from the data/control pin termination to minimize noise.

• The VDDA_PLL supply pin requires a noise minimized 3.3V supply.

Recommended Power Supply Filtering Scheme

The board connections of the various SERDES VDD and VSS pins are critical to system performance. An example

demonstration board schematic is available at www.latticesemi.com.

Power supply ﬁltering is in the form of:

• A parallel bypass capacitor network consisting of 10 µf, 0.1 µf, and 1.0 µf caps close to the power source.

• A parallel bypass capacitor network consisting of 0.01 µf and 0.1 µf close to the pin.

• The decoupling capacitor sizes are important as is the employment of various styles of capacitors. This provides

frequency response coverage across a greater frequency bandwidth. General decoupling guidelines can be

found in Lattice Semiconductor Application Note TN1068.

• Example connections are shown in Figure 101. The naming convention for the power supply sources shown in

the ﬁgure are as follows:

– Supply_1.5 V – All digital, auxiliary power pins.

– Supply_VDDIB – Input RX buffer power pins for SERDES.

– Supply_VDDOB – Output TX buffer power pins for SERDES.

– Supply_VDDANA – TX analog power pins, RX analog power pins, guard band power pins for SERDES.

– Supply_VDD33, VDDA_PLL - FPGA and Embedded PLL power pins.

– Supply VDDA_SPIA, VDDA_SPIB, VDDA_SPIC, VDDA_SPID - Analog core 1.5V SPI supplies.

– Supply VDDH - HSTL output buffer power supply of the QDR Memory Controller.

– Supply REFI_1, REFI_2, REFI_3, REFI_4 - Voltage reference for HSTL input buffer of the QDR Memory

Controller should be one-half VDDH

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