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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ORSPI4 датащи(PDF) 191 Page - Lattice Semiconductor |
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ORSPI4 датащи(HTML) 191 Page - Lattice Semiconductor |
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191 / 263 page  Lattice Semiconductor ORCA ORSPI4 Data Sheet 191 Supported Data Rates The Memory Controller on the ORSPI4 device can support the following data rates. Table 74. Supported Data Rates (36-Bit QDR-II, 32 bit Considered Data) 1. Data Rate = (Max. write data rate + Max. read data rate) for 32 bits of data. 2. Characterized with 200 Mhz rated QDR-II SRAM devices with their DLL enabled. Duty cycle of PMIC and PMICN signals was close to 50%. 3. Assumes board trace lengths of 3 inches or less. Memory Controller Input/Output Timing Specification Figure 99. Memory Controller Output Timing Specifications Table 75. Memory Controller Output Timing Specifications Data Rate -1 -2 -3 Clock Frequency (DDR) Data Rate 1, 2 Clock Frequency (DDR) Data Rate 1, 2 Clock Frequency (DDR) Data Rate 1, 2 156 MHz 19.97 Gbps 3 165 MHz 21.12 Gbps 3 175 MHz 22.40 Gbps 3 Symbol Description Min Value Max Value Units tai PMIK to previous address invalid 1.2 – ns tav PMIK to address valid 2.0 – ns tdi PMIK to previous data invalid 1.0 – ns tdv PMIK to data valid 2.65 – ns DPMIK(N) PMIK/PMINKN duty cycle 40% 60% PMIK/PMIKN Clock Cycle PMIKN PMIA T ai PMID T av T di T dv PMIK D PMIK(N) |
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