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ORCA ORSPI4 Data Sheet

193

Power Supplies for ORSPI4

Power Supply Descriptions

Table 77 shows the ORSPI4 FPGA and embedded core power supply groupings. VDD33 Is a 3.3V positive power

supply used for 3.3 V conﬁguration RAMs. VDD33_FPGAPLL is a 3.3V positive power supply for internal PLLs.

When using PLLs, this power supply should be well isolated from all other power supplies on the board for proper

operation. The ﬁve VDDIO supplies are positive power supply used by the FPGA I/O banks. The 1.5 volt digital

power supplies are used for the FPGA and the embedded core transmit and receive digital logic including the

microprocessor logic. The 1.5 volt analog power supply is used for SERDES high-speed analog circuitry in the

embedded core between the I/O buffers and the digital logic. The SERDES VDDIB and VDDOB power supplies can

be independently set to 1.5 V or 1.8 V, depending on the end application. The SERDES guard band supplies are

independent connection brought out to pins.

Table 77. Power Supplies

The ORSPI4 SPI4 embedded core requires an isolated 1.5V supply connected to four dedicated VDDA_SPI[A:D]

pins. This supply is used to power the analog circuitry of the core between the LVDS I/O and the digital logic. The

LVDS bus also requires connections to pins used for AC center-tap termination. The dedicated LVCTAP pins should

be connected to GND through a 0.01 uFd capacitor.

The QDR memory controller portion of the embedded core has dedicated HSTL I/O buffers which require an addi-

tional 1.5V supply known as VDDH. The HSTL input buffers uses an external reference voltage. The reference volt-

age connects to the REFI_[1:4] pins. The REFI pins should ideally be connected to a noise immune source that is

exactly 1/2 the value of the VDDH supply.

Table 78. Embedded Core Power Supplies

FPGA Supplies

VDD15

VDD33

VDD33_FPGAPLL

VDDIO0

VDDIO1

VDDIO5

VDDIO6

VDDIO7

Supply Description

Name

SERDES Input Buffers (1.5/1.8V)

VDDIB_A

VDDIB_B

VDDIB_C

VDDIB_D

SERDES Guardband (1.5V)

VDDGB

SERDES Output Buffers (1.5/1.8V)

VDDOB_A

VDDOB_B

VDDOB_C

VDDOB_D

SERDES Analog (1.5V)

VDD_ANA

SPI (1.5V)

VDDA_SPIA

VDDA_SPIB

VDDA_SPIC

VDDA_SPID

Memory Controller PLL (3.3V)

VDDA_PLL

HSTL Input Buffer Reference Voltage

(VDDH/2)

REFI_1

REFI_2

REFI_3

REFI_4

HSTL Output Buffer Supply (1.5V)

VDDH

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