ORSPI4 datasheet(188/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

188

SERDES External Reference Clock

The external reference clock selection and its interface are a critical part of system applications for this product.

Table 71 speciﬁes reference clock requirements, over the full range of operating conditions. The designer is

encourage to read TN1040,

SERDES Reference Clock, which discusses various aspects of this system element

and its interconnection.

Table 71. Reference Clock Speciﬁcations (REFCLKP and REFCLKN)

SERDES Core Timing Characteristics

Table 72 summarizes the end-to-end latencies through the embedded core for the various modes. All latencies are

given in clock cycles for system clocks at half the REFCLK_[A:B] frequency. For a REFCLK_[A:B] of 156.25 MHz, a

system clock cycle is 6.4 ns.

Table 72. Signal Latencies, Embedded Core

Parameter

Min.

Typ.

Max.

Units

Frequency Range

—

185

MHz

Frequency Tolerance

-350

—

350

ppm

Duty Cycle (Measured at 50% Amplitude Point)

Rise Time

—

500

1000

Fall Time

—

500

1000

P–N Input Skew

—

Differential Amplitude

500

800

2 x VDDIB

mVp-p

Common Mode Level

Vsingle-ended/2

0.75

VDD15 – (Vsingle-ended/2)V

Single-Ended Amplitude

250

400

VDDIB

mVp-p

Input Capacitance (at REFCLKP)

—

Input Capacitance (at RECLKN)

—

1. This speciﬁcation indicates the capability of the high-speed receiver CDR PLL to acquire lock when the reference clock frequency and

incoming data rate are not synchronized.

Operating Mode

Signal Latency (max.)

Transmit Path

5 clock cycles

Receive Path

Multi-Channel Alignment Bypassed

4.5 clock cycles

With Multi-Channel Alignment

13.5-22.5 clock cycles

1. With multi-channel alignment, the latency is largest when the skew between channels is at the maximum that can be correctly

compensated for (18 clock cycles). The latency speciﬁed in the table is for data from the channel received ﬁrst.

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