ORSPI4 datasheet(186/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

186

SERDES High Speed Data Receiver

Table 68 speciﬁes receiver parameters measured on devices with worst case process parameters and over the full

range of operation conditions.

Table 68. External Data Input Speciﬁcations

Input Data Jitter Tolerance

A receiver's ability to tolerate incoming signal jitter is very dependent on jitter type. High speed serial interface stan-

dards have recognized the dependency on jitter type and have recently modiﬁed speciﬁcations to indicate toler-

ance levels for different jitter types as they relate to speciﬁc protocols (e.g XAUI, FC, Inﬁniband etc.). Sinusoidal

jitter is considered to be a worst case jitter type. Table 69 shows receiver speciﬁcations with 10 MHz sinusoidal jit-

ter injection. XAUI speciﬁc jitter tolerance measurements were measured in a separate experiment detailed in tech-

nical note TN1032,

SERDES Test Chip Jitter, and are not reﬂected in these results.

Table 69. Receiver Sinusoidal Jitter Tolerance Speciﬁcations

Parameter

Conditions

Min.

Typ.

Max.

Units

Input Data

Stream of Nontransitions

8b/10b encode/decode off

—

Bits

Sensitivity (differential), worst-case

3.125 Gbps

—

mVp-p

Input Levels

—VSS - 0.3

—

VDD_ANA + 0.3

Internal Buffer Resistance (Each input to VDDIB)

—

Ω.

PLL Lock Time

—

Note 3

—

1. With PRBS 2^7-1 data pattern, all channels operating, FPGA logic active, REFCLK jitter of 30 ps., TA = 0

oC to 85oC, 1.425 V to 1.575 V sup-

ply.

2. Input level min + (input peak to peak swing)/2

≤ common mode input voltage ≤ input level max - (input peak to peak swing)/2

3. The ORSPI4 SERDES receiver performs four levels of synchronization on the incoming serial data stream, providing ﬁrst bit, then byte

(character), then channel (32-bit word), and ﬁnally optional multi-channel alignment as described in TN1025. The PLL Lock Time is the time

required for the CDR PLL to lock to the transitions in the incoming high-speed serial data stream. If the PLL is unable to lock to the serial

data stream, it instead locks to REFCLK to stabilize the voltage-controlled oscillator (VCO), and periodically switches back to the serial data

stream to again attempt synchronization.

Parameter

Conditions

Max.

Unit

Input Data

Jitter Tolerance @ 3.125 Gbps, Typical

600 mV diff eye

0.75

UIP-P

Jitter Tolerance @ 3.125 Gbps, Worst case

600 mV diff eye

0.65

UIP-P

Jitter Tolerance @ 2.5 Gbps, Typical

600 mV diff eye

0.79

UIP-P

Jitter Tolerance @ 2.5 Gbps, Worst case

600 mV diff eye

0.67

UIP-P

1. With PRBS 2^7-1 data pattern, all channels operating, FPGA logic active, REFCLK jitter of 30 ps., TA = 0

oC to 85oC, 1.425 V

to 1.575 V supply. Jitter measured with a Wavecrest SIA-3000.

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