ORSPI4 datasheet(126/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

126

(LOS) state in the word alignment state machines. Since these signals come from the DEMUX block, if multi-chan-

nel alignment is enabled, the code violation signals correspond to data that must still be multi-channel aligned.

Hence these signals provide advance notiﬁcation of detected violations in data that will appear at the core/FPGA

interface several clock cycles later. The exact number of clock cycles that the data is delayed depends on the skew

between the incoming data for the different channels.

Multi-Channel Alignment Clocking Strategies for the ORSPI4

The data on the four channels SERDES can be independent of each other or can be synchronized in several ways.

For example, two channels within the SERDES can be aligned together; channel A and B and/or channel C and D.

Alternatively, all four channels in a SERDES quad can be aligned together to form a communication channel with a

bandwidth of 10 Gbits/s. Individual channels within an alignment group can be disabled (i.e., powered down) with-

out disrupting other channels. Clocking strategies for these various modes are described in the following para-

graphs.

For dual alignment, both twins within a quad can be sourced by clocks that are different from the other channels,

however each pair of SERDES must have the same clock. The channel pair A and B is driven on the low-speed

side by RSYS_CLK_1 and the channel pair C and D are driven on the low-speed side by RSYS_CLK_2. Either

RWCKA or RWCAB can be connected to RSYS_CLK_1, and either RWCKC or RWCKD can be connected to

RSYS_CLK_2. A clocking example for dual alignment is shown in Figure 65.

Figure 65. Receive Clocking for a Dual Alignment in a Single Quad

Common Logic

Channel A

Channel B

Channel D

Channel C

REFCLK[P:N]

156.25 MHz

RCK78

RWCKA

RWCKC

RSYS_CLK_1

RSYS_CLK_2

FPGA

Logic

Two Bidirectional Channels

of 3.125 Gbits/s

Serial Data

RWCKB

RWCKD

All Clocks at

78.125 MHZ

TCK78

TSYS_CLK_A

TSYS_CLK_B

TSYS_CLK_C

TSYS_CLK_D

Two Bidirectional Channels

of 3.125 Gbits/s

Serial Data

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