| поискавой системы для электроныых деталей |
|
ORSPI4 датащи(PDF) 123 Page - Lattice Semiconductor |
|
|
|||||||||||||||||||||||||||||
ORSPI4 датащи(HTML) 123 Page - Lattice Semiconductor |
|
123 / 263 page ![]() Lattice Semiconductor ORCA ORSPI4 Data Sheet 123 RWBIT8_x indicates the presence of a Km.n control character in the receive data byte. Only RWBIT8_x and RWD_x inputs are stored in the FIFO. During alignment process, RALIGN[3]_x is used to synchronize multiple channels. If a channel is not in any alignment group, it will set the FIFO-write-address to the beginning of the FIFO, and will set the FIFO-read-address to the middle of the FIFO, at the first assertion of RALIGN[3]_x after reset or after the resync command. The ORSPI4 has a total of four SERDES channels. The incoming data of these channels can be synchronized in several ways or can be independent of one another. Two SERDES channels can be aligned together. Channel A and B and/or channel C and D can form a pair as shown in Figure 62. Alternately, all four SERDES channels can be aligned together to form a communication channel with a bandwidth of 10 Gbits/s as shown in Figure 63. Indi- vidual channels within an alignment group can be disabled (i.e., powered down) without disrupting other channels. Figure 62. Twin Channel Alignment Figure 63. Alignment of SERDES Quad (4-Channels) For every alignment group, there are both an OVFL and an OOS status register bit. The OVFL bit is set when align- ment FIFO overflow occurs. The OOS bit is flagged when the down counter in the synchronization algorithm has reached a value of 0 and alignment characters from all channels within an alignment group have not been received. XAUI Lane Alignment Function (Lane Deskew) In XAUI mode, the receive section in each lane uses the /A/ code group to compensate for lane-to-lane skew. The mechanism restores the timing relationship between the four lanes by lining up the /A/ characters into a column. Figure 64 shows the alignment of four lanes based on /A/ character. A minimum spacing of 16 code-groups implies that at least ± 80 bits of skew compensation capability should be provided, which the ORSPI4 significantly exceeds. Channel A Channel B Channel C Channel D Channel A Channel B Channel C Channel D t1 t0 Twin alignment of channels A and B Twin alignment of channels C and D Channel B Channel C Channel D Channel A Channel B Channel C Channel D Channel A Quad alignment of channels A. B, C and D t0 |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |