ORSPI4 datasheet(119/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

119

These are derived from the recovered low-speed complementary clocks from the SERDES blocks. RWCK_A

belongs to Channel A, RWCK_B belongs to channel B and so on. With a reference clock input of 156.25 MHz,

these clocks operate at 78.125 MHz.

RCK78:

These are muxed outputs of RWCKA[A:D] and RWCKB[B:D] respectively. With a reference clock input of 156.25

MHz, these clocks operate at 78.125 MHz.

RSYS_CLK_[1:2]

These clocks are inputs to the SERDES. These are used by each channel as the read clock to read received data

from the alignment FIFO within the SERDES. To guarantee that there is no overﬂow in the alignment FIFO, it is an

absolute requirement that the write and read clocks be frequency locked to 0 ppm. Examples of how to achieve this

are shown in the section on recommended board-level clocking.

TCK78:

This is a muxed output from the core to the FPGA across the core-FPGA interface of one of the four transmit SER-

DES clocks operating at up to 92.5 MHz in the SERDES.

TSYS_CLK[A:D]:

These clocks are inputs to the SERDES from the FPGA. These are used by each channel to control the timing of

the Transmit Data Path. To guarantee correct transmit operation, these clocks must be frequency locked within 0

ppm to TCK78.

List of Operating Modes SERDES

Transmit and Receive Clock Rates

Table 31 shows typical relationship between the data rates, the reference clock, the transmit TCK78 clock and the

receive RCK78 clock. The selection of full-rate or half-rate for a given reference clock speed is set by bits in the

transmit and receive control registers, and can be set on a per-channel basis.

Table 31. Transmit Data and Clock Rates

Mixing Half-rate, Full-rate Modes

When channel alignment is enabled, all receive channels within an alignment group should be conﬁgured at the

same rate. For example, channels A and B, can be conﬁgured for twin alignment and full-rate mode, while channels

C and D can be conﬁgured for half-rate mode. In quad alignment mode, all four channels must be conﬁgured in

either half or full-rate mode. Register settings for multi-channel alignment are described in a later section.

Besides taking in a TSYS_CLK_x from the FPGA logic for each channel, the transmit path logic sends back a clock

of the same frequency, but arbitrary phase. This clock, TCK78, is derived from the MUX block of one of the 2 chan-

nels in its SERDES block. The MUX blocks provide the potential source for TCK78 by a divide-by-4 of the SERDES

STBC311xs clock used in synchronizing the transmit data words in the STBC311x clock domain. The STBC311x

clocks are internal to the core and are not brought across the core/FPGA interface

Data Rate

Reference Clock

TCK78[A: B] and

RCK78[A:B] Clocks

Rate of Channel

Selected as Clock

Source

0.6 Gbits/s

60 MHz

15 MHz

Half

1.0 Gbits/s

100 MHz

25 MHz

Half

1.25 Gbits/s

125 MHz

31.25 MHz

Half

2.0 Gbits/s

100 MHz

50 MHz

Full

2.5 Gbits/s

125 MHz

62.5 MHz

Full

3.125 Gbits/s

156 MHz

78 MHz

Full

3.7 Gbits/s

185 MHz

92.5 MHz

Full

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