ORSPI4 datasheet(114/263 Pages) LATTICE

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ORCA ORSPI4 Data Sheet

114

The NOWDALGN_x bit is a level-sensitive bit. If it is a “1”, then the DEMUX does not dynamically alter the word

boundary based on comma and SWDSYNC_x output of the SERDES. This might be useful if a channel were con-

ﬁgured to bypass the multi-channel alignment FIFO and raw 40-bits of data are directed from SERDES to FPGA.

In Fibre Channel mode, the default setting (NOWDALGN_x = 0) causes the word boundary to be set as soon as

the SERDES SWDSYNC_x output is a “1” and a comma character has been detected. The character that is the

comma becomes the most-signiﬁcant portion of the demultiplexed word. When the SERDES loses link synchroni-

zation it will drop SWDSYNC_x low. The DEMUX will begin search for word alignment as soon as SWDSYNC_x

goes to “1” again.

The DEMUX passes on to the channel alignment FIFO block a set of control signals that indicate the location of the

synchronizing event. RALIGN_x[3:0] are these indicators. If there is no link synchronization, all of the

RALIGN_x[[3:0] bits will be zeros independent of synchronizing events that come in. When the link is synchronized,

then the bit that corresponds to the time of the synchronization event will be set to a “1”. The relationship between

a time sequence of values input at SRBDx[7:0] to the values output at RWD_x[39:0] is shown in Figure 54. A paral-

lel relationship exists between SRBDx[8] and RWBIT8_x[3:0] as well as between SRBD_x[9] and RWBIT9_x[3:0].

Figure 54. Receive DEMUX Block for a Single SERDES Channel. (NOTE: xx = A, B, C, or D)

One clock per block of two or four channels, called RCK78, is sent to the FPGA. The control bits RCKSEL[A,B] are

used to select the channel that is the source for these clocks.

Link State Machines

Two link state machines are included in each SERDES channel; one for XAUI applications and a second for Fibre

Channel applications.

The Fibre Channel link state machine is responsible for establishing a valid link between the transmitter and the

receiver and for maintaining link synchronization. The machine is initially in the loss of synchronization (LOS) state

upon power-on reset. This is indicated by WDSYNC_x = 0. While in this state, the machine looks for a particular

number of consecutive idle ordered sets without any invalid data transmission in between before declaring syn-

chronization achieved. Achievement of synchronization is indicated by asserting WDSYNC_x = “1”. Speciﬁcally, the

machine looks for three continuous idle ordered sets without any misaligned comma character or any running dis-

parity based code violation in between. In the event of any such code violation, the machine would reset itself to the

pppp

SRBDxx[9:0]

10-bit

40-bit

RWD_XX[31:24]

RWD_XX[23:16]

RWD_XX[15:8]

RWD_XX[7:0]

LATENCY = 4 RSYS_CLK [A1,...,B2] CLOCKS

7-0

RWBIT8_XX[3]

RWBIT9_XX[3]

RWBIT8_XX[2]

RWBIT8_XX[1]

RWBIT8_XX[0]

RWBIT9_XX[2]

RWBIT9_XX[1]

RWBIT9_XX[0]

7-0

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