ORSPI4 datasheet(113/263 Pages) LATTICE

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ORCA ORSPI4 Data Sheet

113

frequency. With the 8b10bR_x control bit of the SERDES channel set to “1”, the data presented at SRBD_x[9:0] will

be decoded characters. Bit 8 will indicate whether SRBDx[7:0] represents an ordinary data character (bit 8 = 0), or

whether SRBD_x[7:0] represents a special character, like a comma. Bit 9 may be either a code violation indicator

or one of seven out of synchronization state indicators, as described later.

Figure 53. Receive Path Timing for a Single SERDES Channel. (NOTE: xx = A, B, C, or D)

When 8b10bR is set to “0”, the data at SRBD_x[9:0] will not be decoded. The XAUI link-state machine should not

be used in this mode of operation. When in XAUI mode, the MUX/DEMUX looks for /A/ (as deﬁned in IEEE 802.3ae

v.2.1) characters for channel alignment and requires the characters to be in decoded form for this to work

1:4 Demultiplexer (DEMUX)

The 1:4 DEMUX has to accumulate four sets of characters presented to it at the SERDES receive interface and put

these out at one time at the low-speed receive interface.

Another task of the 1:4 DEMUX is to recognize the synchronizing event and adjust the 4-byte boundary so that the

synchronizing character leads off a new 4-byte word. In Fibre Channel mode, this synchronizing character is a

comma. This feature will be referred to as DEMUX word alignment in other areas of this document. DEMUX word

alignment will only occur when the communication channel is synchronized. When there is no synchronization of

the link, the 1:4 DEMUX will continue to output 4-byte words at some arbitrary, but constant, boundary. There are 2

control register bits available for each channel for word alignment. They are DOWDALGN_x and NOWDALGN_x.

The DOWDALGN_x bit is positive edge triggered. Writing a 0 followed by a “1” to this register bit will cause the cor-

responding DEMUX to look for a new comma character and align the 32-bit word such that the comma is in the

most signiﬁcant byte position. It is important that the comma is in the most signiﬁcant byte position since the multi-

channel aligner looks for comma in the most signiﬁcant byte only.

Typically, it is not necessary to set the DOWDALGN_x bit. When the link state machine loses synchronization

(DEMUXWAS_x register bit is 0), the DEMUX block automatically looks for a new comma character irrespective of

whether the DOWDALGN_x bit is set or not. However, as discussed earlier, the comma character may become

misaligned without the Fibre Channel link state machine indicating a loss of synchronization. In such cases, the

DOWDALGN_x bit must be toggled to force resynchronization.

EMBEDDED CORE

.....

..... PQ R S T X Y Z

SRBDX[9:0]

.....

SRBC0X

SRBC1X

.....

SBYTSYNCX,

SVCX

SWDSYNCX

.....

HDINx

SRBDX[9:0]

1-bit

10-bit

.....

LATENCY =

APPROX 23 CLOCKS

.....

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