ORSPI4 datasheet(118/263 Pages) LATTICE

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ORCA ORSPI4 Data Sheet

118

nents in the DC to 5 MHz range should be minimized. The required electrical characteristics for the reference clock

are given in Table 71.

Note: In sections of this data sheet, the differential clocks are simply referred to as the reference clock as REFCLK.

Synthesized and Recovered Clocks

The SERDES block contains its own dedicated PLLs for transmit and receive clock generation. The user provides a

reference clock of the appropriate frequency, as described in the previous section. The transmitter PLL uses the

REFCLK inputs to synthesize the internal high-speed serial bit clocks. The receiver PLLs extract the clock from the

serial input data and retime the data with the recovered clock. The receive PLL for each channel has two modes of

operation - lock to reference and lock to data with retiming.

When no data or invalid data is present on the HDINP_x and HDINN_x pins, the receive VCO will not lock to data

and its frequency can drift outside of the nominal ±350 ppm range. Under this condition, the receive PLL will lock to

REFCLK for a ﬁxed time interval and then will attempt to lock to receive data. The process of attempting to lock to

data, then locking to clock will repeat until valid input data exists. There is also a control register bit per channel to

force the receive PLL to always lock to the reference clock.

The high-speed transmit and receive serial data links can run at 0.6 to 3.7 Gbits/s, depending on the frequency of

the reference clock and the state of the control bits from the internal transmit control register. The interface to the

serializer/deserializer block runs at 1/10th the bit rate of the data lane. Additionally, the MUX/DEMUX logic converts

the data rate and bit-width so the FPGA core can run at 1/4th this frequency, which gives a range of 15 to 92.5 MHz

for the data in and out of the FPGA.

Internal Clock Signals at the FPGA/Core SERDES Interface

There are several clock signals deﬁned at the FPGA/SERDES interface in addition to the external reference clock.

All of the SERDES clock signals are shown in Figure 57 and are described following the paragraphs.

Figure 57. SERDES Clock Signals (High-Speed Serial I/O Also Shown)

REFCLKP, REFCLKN:

These are the differential reference clocks provided to the ORSPI4 device as described earlier. They are used as

the reference clock for both TX and RX paths. For operation of the serial links at 3.125 Gbits/s, the reference clocks

will be at a frequency of 156.25 MHz.

RWCK[A:D]:

These are the low-speed receive clocks from the SERDES to the FPGA across the core-FPGA interface.

Common Logic

Channel A

Channel B

Channel D

Channel C

RCK78

TCK78

RSYS_CLK_1

TSYS_CLK_A

RWCKA

RWCKB

TSYS_CLK_B

RWCKC

TSYS_CLK_C

RSYS_CLK_2

TSYS_CLK_D

RWCKD

REFCLK[P:N]

HDIN[P:N]

HDOUT[P:N]

HDIN[P:N]

HDOUT[P:N]

HDIN[P:N]

HDOUT[P:N]

HDIN[P:N]

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