ORSPI4 datasheet(109/263 Pages) LATTICE

109 / 263 page

Lattice Semiconductor

ORCA ORSPI4 Data Sheet

109

Figure 50. TRANSMIT MUX Block Timing - Single Channel. (NOTE: xx = A, B, C, or D)

SERDES Block

The SERDES block accepts either 8-bit data to be encoded or 10-bit unencoded data at the parallel input port from

the MUX/DEMUX block. It also accepts the reference clock at the REFCLK input and uses this clock to synthesize

the internal high-speed serial bit clock.

The internal STBC311x clock is derived from the reference clock. The frequency of this clock depends on the set-

ting of the half-rate/full-rate control bit setting the mode of the SERDES and the frequency of the REFCLK and/or

that of the high-speed serial data. A falling edge on the STBC311x clock port will cause a new data character to be

transferred into the SERDES block. The latency from the SERDES block input to the high-speed serial output is ﬁve

STBC311x clock cycles, as shown in Figure 51.

Figure 51. Transmit Path Timing - Single SERDES Channel (NOTE: xx = A, B, C, or D)

Each block also sends a clock to the FPGA logic. This clock, TCK78[A,B], is sourced from one of the four MUX

blocks and has the same frequency as TSYS_CLK_x, but arbitrary phase. Within each MUX block, the low fre-

quency clock output is obtained by dividing by four, the SERDES STBC311x clock, which is used internally to syn-

chronize the transmit data words. TCKSEL control bits select the channel to source TCK78. The internal signals

STBDx[9:0] (where x is represents A, B, C or D) from the MUX block carry unencoded character data and control

bits. The 10th bit (STBDx[9]) of each data lane into the SERDES is used to force a negative disparity present state.

xyz

STBDxx[9:0]

LATENCY = 4 TSYS_CLK_xx CLOCKS

TWDxx[31:24],

TSYS_CLK_xx

10-bit wide data

TWDxx[23:16],

TWDxx[15:8],

TCOMMAxx[3]

TCOMMAxx[2]

TCOMMAxx[1]

TCOMMAxx[0]

TWDxx[7:0],

TBIT9xx[0]

TBIT9xx[1]

TBIT9xx[2]

TBIT9xx[3]

p7-0 p8

t7-0 t8

q7-0 q8

x7-0 x8

r7-0 r8

y7-0 y8

s7-0 s8

z7-0 z8

STBDxx[9:0]

STBC311xx

HDOUT_xx

LATENCY =

5 STBC311x CLOCKS

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