L6722

12 Layout guidelines

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Remote Sense Connection must be routed as parallel nets from the FBG/FBR pins to the load

in order to avoid the pick-up of any common mode noise. Connecting these pins in points far

from the load will cause a non-optimum load regulation, increasing output tolerance.

Locate current reading components close to the device. It's also important to minimize any

offset in the measurement and, to get a better precision, to connect the traces as close as

possible to the sensing elements.

Caution:

Boot capacitor extra charge. Systems that do not use Schottky diodes in parallel to the low-

side mosfet might show big negative spikes on the phase pin. This spike can be limited as well

as the positive spike but has an additional consequence: it causes the bootstrap capacitor to be

over-charged. This extra-charge can cause, in the worst case condition of maximum input

voltage and during particular transients, that boot-to-phase voltage overcomes the abs. max.

ratings also causing device failures. It is then suggested in this cases to limit this extra-charge

by:

–

adding a small resistor in series to the boot diode (one resistor can be enough for all

the three diodes if placed upstream the boot diode anode, see Figure 18)

–

using non-capacitive boot diodes (such as standard diodes).

Figure 18. Power connections and related connections layout (same for all phases).

L

UGATEx

PHASEx

LGATEx

PGNDx

LOAD

BOOTx

PHASEx

VCC

SGND

+Vcc

L

LOAD

To limit C

BOOT

Extra-Charge