ADIS16365

Preliminary Technical Data

Rev. PrA | Page 14 of 20

Dynamic Range

There are three dynamic range settings: ±75°/sec, ±150°/sec,

and ±300°/sec. The lower dynamic range settings (75, 150) limit

the minimum filter tap sizes to maintain the resolution as the

measurement range decreases. The recommended order for

programming the SENS/AVG register is upper byte (sensitivity),

followed by lower byte (filtering). The contents of the

SENS/AVG register are nonvolatile.

Table 15. SENS/AVG Bit Descriptions

Bits

Value

Description

(Default = 0x0000)

[15:11]

Not used

[10:8]

Measurement range (sensitivity) selection

100

300°/sec (default condition)

010

150°/sec, filter taps ≥ 4 (Bits[2:0] ≥ 0x02)

001

75°/sec, filter taps ≥ 16 (Bits[2:0] ≥ 0x04)

[7:3]

Not used

[2:0]

INPUT/OUTPUT FUNCTIONS

The ADIS16365 provides several input/output functions,

including a 12-bit ADC, a 12-bit DAC, and four general

purpose, digital input/output lines that have several

configuration options.

Auxiliary ADC

The auxiliary ADC is a standard 12-bit ADC that digitizes other

system-level analog signals. The output of the ADC can be moni-

tored through the AUX_ADC register, as defined in Table 8.

The ADC is a 12-bit successive approximation converter. The

output data is presented in straight binary format with the full-

scale range extending from 0 V to 3.3 V.

Figure 17 shows the equivalent circuit of the analog input

structure of the ADC. The input capacitor (C1) is typically 4 pF

and can be attributed to parasitic package capacitance. The two

diodes provide ESD protection for the analog input. Care must

be taken to ensure that the analog input signals are never outside

the range of −0.3 V to +3.5 V. Signals outside this range cause

the diodes to become forward-biased and to start conducting.

The diodes can handle 10 mA without causing irreversible

damage. The resistor is a lumped component that represents

the on resistance of the switches. The value of this resistance is

typically 100 Ω. Capacitor C2 represents the ADC sampling

capacitor and is typically 16 pF.

VCC

C2

C1

R1

D

D

Figure 17. Equivalent Analog Input Circuit

Conversion Phase: Switch Open

Track Phase: Switch Closed

For ac applications, it is recommended that high frequency

components from the analog input signal be removed by using

a low-pass filter on the analog input pin.

In applications where harmonic distortion and signal-to-noise

ratios are critical, the analog input must be driven from a low

impedance source. Large source impedances significantly affect

the ac performance of the ADC. This can necessitate the use of

an input buffer amplifier. When no input amplifier is used to drive

the analog input, the source impedance should be limited to

values lower than 1 kΩ.

Auxiliary DAC

The auxiliary DAC provides a 12-bit level adjustment function.

The AUX_DAC register controls the operation of the auxiliary

DAC function, which is useful for systems that require analog

level controls. It offers a rail-to-rail buffered output that has a

range of 0 V to 3.3 V. The DAC can drive its output to within

5 mV of the ground reference when it is not sinking current.

As the output approaches ground, the linearity begins to degrade

(100 LSB beginning point). As the sink current increases, the

nonlinear range increases. The DAC output latch function,

contained in the COMMAND register, provides continuous

operation while writing to each byte of this register. The

contents of this register are volatile, which means that the

desired output level must be set after every reset and power

cycle event.

Table 16. AUX_DAC Bit Descriptions

Bit

Description

(Default = 0x0000)

[15:12]

Not used

[11:0]

Data bits, scale factor = 0.8059 mV/code

Offset binary format, 0 V = 0 codes