ADIS16365SLASHPCBZ datasheet(4/20 Pages) AD

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ADIS16365

Preliminary Technical Data

Rev. PrA | Page 4 of 20

Parameter

Conditions

Min

Typ

Max

Unit

ADC INPUT

Resolution

Bits

Integral Nonlinearity

±2

LSB

Differential Nonlinearity

±1

LSB

Offset Error

±4

LSB

Gain Error

±2

LSB

Input Range

+3.3

Input Capacitance

During acquisition

DAC OUTPUT

5 kΩ/100 pF to GND

Resolution

Bits

Relative Accuracy

For Code 101 to Code 4095

±4

LSB

Differential Nonlinearity

±1

LSB

Offset Error

±5

Gain Error

±0.5

Output Range

+3.3

Output Impedance

Output Settling Time

μs

LOGIC INPUTS1

Input High Voltage, VINH

2.0

Input Low Voltage, VINL

0.8

CS signal to wake up from sleep mode

0.55

Logic 1 Input Current, IINH

VIH = 3.3 V

±0.2

±10

μA

Logic 0 Input Current, IINL

VIL = 0 V

All Except RST

−40

−60

μA

RST

−1

Input Capacitance, CIN

DIGITAL OUTPUTS1

Output High Voltage, VOH

ISOURCE = 1.6 mA

2.4

Output Low Voltage, VOL

ISINK = 1.6 mA

0.4

SLEEP TIMER

Timeout Period2

0.5

128

Sec

FLASH MEMORY

Endurance3

10,000

Cycles

Data Retention4

TJ = 85°C

Years

START-UP TIME5

Time until data is available

Power-On

Fast mode, SMPL_PRD ≤ 0x07

TBD

Normal mode, SMPL_PRD ≥ 0x08

TBD

Reset Recovery

Fast mode, SMPL_PRD ≤ 0x07

TBD

Normal mode, SMPL_PRD ≥ 0x08

TBD

Sleep Mode Recovery

TBD

CONVERSION RATE

Sample Rate Settings

SMPL_PRD = 0x01 to 0xFF

0.413

819.2

SPS

Clock Accuracy

TBD

SYNC Input Clock

1.2

kHz

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