Preliminary Technical Data

ADIS16365

Rev. PrA | Page 13 of 20

OPERATION CONTROL REGISTERS

Global Commands

In addition to the calibration commands, the COMMAND

register provides initiation bits for several other common

functions. Writing a 1 to the assigned COMMAND bit exercises

its function.

Table 12. COMMAND Bit Descriptions

Bits

Description

[15:8]

Not used

[7]

Software reset command

[6:5]

Not used

[4]

Precision autonull command

[3]

Flash update command

[2]

Auxiliary DAC data latch

[1]

Factory calibration restore command

[0]

Autonull command

The software reset command restarts the internal processor, which

loads all registers with the contents in their flash memory locations.

The flash update copies the contents of all flash backup registers

into their assigned, nonvolatile, flash memory locations. This

process takes approximately 50 ms and requires a power supply

that is within the specified operating range. After waiting the

appropriate time for the flash update to complete, verify successful

completion by reading the STATUS register. If the flash update

is successful, the flash update error is 0. If the flash update is not

successful, reading this error bit accomplishes two things: (1)

alerting the system processor to try again, and (2) clearing the

error flag, which is required for flash memory access.

The DAC data latch command loads the contents of AUX_DAC

into the DAC latches. Because the AUX_DAC contents must be

updated one byte at a time, this command ensures a stable DAC

output voltage during updates.

Finally, reading the COMMAND register (see

Figure 4) starts the burst mode read sequence.

Internal Sample Rate

The SMPL_PRD register controls the ADIS16365 internal sample

rate and has two parts: a selectable time base and a multiplier. The

following relationship produces the sample rate:

Table 13. SMPL_PRD Bit Descriptions

Bit

Description

(Default = 0x0001)

[15:8]

Not used

[7]

Time base, 0 = 0.61035 ms, 1 = 18.921 ms

[6:0]

An example calculation of the default sample period follows:

SMPL_PRD = 0x03, B7 − B0 = 00000011 ->

The contents of this register determine whether the device is in

fast mode or low power mode.” Fast mode occurs when the

contents of SMPL_PRD are less than 0x0A. Refer to Table 1 and

Table 2 for the performance trade-offs associated with each mode.

Setting SMPL_PRD = 0x000 activates the external clock.

Power Management

In addition to offering two different performance modes for

power optimization, the ADIS16365 offers a programmable

shutdown period that the SLP_CNT register controls.

Table 14. SLP_CNT Bit Descriptions

Bit

Description

(Default = 0x0000)

[15:8]

Not used

[7:0]

Data bits, 0.5 seconds/LSB (0x08, sleep time = 4 sec)

Once in sleep mode, a reset or power cycle is required to wake up.

Digital Filtering

The signal conditioning circuit of each sensor has an analog

bandwidth of approximately 350 Hz. A programmable-length

Bartlett window FIR filter provides opportunity for additional

noise reduction on all output data registers. The SENS/AVG

register controls the number of taps in power-of-two step sizes,

from zero to six.

Filter setup requires one simple step: write the appropriate M

factor to the assigned bits in the SENS/AVG register. The bit

assignments are listed in Table 15. The frequency response

relationship for this filter is

(

)

()

s

s

A

A

B

t

f

N

t

f

N

f

H

f

H

f

H

×

×

π

×

×

π

=

=

sin

sin

)

(

)

(

)

(

2

× ×

0

–20

–40

–60

–80

–100

–120

–140

0.001

0.01

0.1

1

FREQUENCY (

N = 2

N = 4

N = 16

N = 64

Figure 16. Bartlett Window FIR Frequency Response