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ADIS16365/PCBZ датащи(PDF) 6 Page - Analog Devices

номер детали ADIS16365/PCBZ
подробное описание детали  Tri-Axis Inertial Sensor
PDF  20 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
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ADIS16365/PCBZ датащи(HTML) 6 Page - Analog Devices

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ADIS16365
Preliminary Technical Data
Rev. PrA | Page 6 of 20
TIMING SPECIFICATIONS
TA = 25°C, VDD = +5 V, unless otherwise noted.
Table 2.
Fast Mode
(SMPL_PRD < 0x09)
Low Power Mode
(SMPL_PRD > 0x0A)
Burst Mode
Parameter
Description
Min1
Typ
Max
Min1
Typ
Max
Min1
Typ
Max
Unit
fSCLK
0.01
2.0
0.01
0.3
0.01
1.0
MHz
tSTALL
Stall period between data
9
75
1/fSCLK
μs
tCS
Chip select to clock edge
48.8
48.8
48.8
ns
tDAV
DOUT valid after SCLK edge
100
100
100
ns
tDSU
DIN setup time before SCLK rising edge
24.4
24.4
24.4
ns
tDHD
DIN hold time after SCLK rising edge
48.8
48.8
48.8
ns
tSCLKR, tSCLKF
SCLK Rise/Fall times
5
12.5
5
12.5
5
12.5
ns
tDF, tDR
DOUT rise/fall times
5
12.5
5
12.5
5
12.5
ns
tSFS
CS high after SCLK edge
5
5
5
ns
1Guaranteed by design, not tested.
TIMING DIAGRAMS
CS
SCLK
DOUT
DIN
1
2
3
4
5
6
15
16
W/R
A5
A4
A3
A2
D2
MSB
DB14
D1
LSB
DB13
DB12
DB10
DB11
DB2
LSB
DB1
tCS
tSFS
tDAV
tDSU
tDHD
Figure 2. SPI Timing and Sequence
CS
SCLK
DIN
W/R
A5
A4
A3
A2
A1
A0
DC7
DC6
DC5
DC4
DC3
DC2
DC1
DC0
DATA FRAME
WRITE = 1
READ = 0
REGISTER ADDRESS
DATA FOR WRITE COMMANDS
DON’T CARE FOR READ COMMANDS
W/R
A5
A4
A3
A2
A1
A0
DC7
DC6
DC5
DC4
DC3
DC2
DC1
DC0
DATA FRAME
tSTALL
DATA FROM PREVIOUS SEQUENCE
DOUT
Figure 3. DIN Bit Sequence
0x3E00
PREVIOUS
DON’T CARE
SUPPLY_OUT
XGYRO_OUT
ZTEMP_OUT
123
11
12
AUX_ADC
YGYRO_OUT
ZGYRO_OUT
45
SCLK
DOUT
DIN
CS
Figure 4. Burst Mode Read Sequence



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