ADIS16365

Preliminary Technical Data

Rev. PrA | Page 10 of 20

BASIC OPERATION

The ADIS16365 runs off an internal clock and requires no

external initialization. Once the power supply reaches 4.75 V,

the ADIS16365 executes an internal initialization sequence and

then starts producing data. At this point, the DIO1 will start

pulsing as well, repeating each time new data loads into the

output registers. This data-ready signal serves as an interrupt

service signal, telling the system processor that the device is

awake and producing data.

VCC

DIO1

Figure 13. Start-Up Sequence

PHYSICAL INSTALLATION

The ADIS16365 provides slots on each side for attachment.

These slots accommodate either 2-56 or 2 mm machine screws.

Attach the body of the ADIS16365 to the proper surface prior to

inserting the electrical connector, which is located at the end of

the flex.

DRILL AND TAP FOR

2mm MACHINE SCREWS.

2×

FOR 1.5mm

ALIGNMENT PINS.

2×

ALIGNMENT PINS FOR

SAMTEC CLM-112-02-LM-D-A.

2×

4

BSC

26.700

BSC

0.500 BSC

2×

4

BSC

27.700

BSC

8.350

10

16.810

2×

Figure 14. Typical Hole Pattern for the ADIS16365 Attachment

INITIAL HOOK-UP AND CONFIGURATION

The electrical connection uses a 24-pin header that mates to

either the CLM or MLE family of connectors from Samtec. The

evaluation system for this product uses Samtec part number:

CLM-112-02-LM-D-A. Samtec is the appropriate source for

suggested pad layout geometries for this mating connector.

Although this device runs off a +5 V power supply, the digital

lines are compatible with +3.3 V-digital I/O systems.

SCLK

MOSI

IRQ

MISO

SS

3.3V

MICROCONTROLLER/

DSP/FPGA

SCLK

DIN

DIO1

DOUT

CS

5V

ADIS16365

Figure 15. Electrical Hook-Up Diagram

All of the output data and configuration options have 16-bit

registers assigned to govern their operation. Each byte has its

own unique 6-bit address, which provides user access using the

serial peripheral interface (SPI). While SPI is a common digital

interface, most digital processor platforms accommodate

several configuration options. The parameters listed in Table 6

are configuration options that SPI-compatible digital processor

platforms offer in configuration registers. This table is a guide

for determining how to configure them for communication

with the ADIS16365.

Table 6. Typical Processor SPI Configuration Settings

Processor Setting

Notes

Master

The ADIS16365 operates as a slave.

SCLK Rate < 2MHz

(See Table 2)

Derived from a master clock, which is

divided down to meet this requirement.

CPOL = 1

Clock polarity.

CPHA = 1

Clock phase.

MSB-first

Bit sequence.

16-bit data cycles

For an 8-bit processor, this requires two

back-to-back 8-bit spi_read commands,

while keeping the chip-select line low.

DATA COLLECTION

The ADIS16365 produces data outputs in 16-bit segments,

based on the previous 16-bit configuration sequence. The bit

assignments for the configuration sequence are in Figure 3. For

a read command, only the first eight bits require definition. The

first two bits are zero, and the next six bits represent the register’s

lower byte, listed in Table 7. When using 8-bit microcontrollers,

use two back-to-back SPI read calls, while keeping the chip

select line low. A typical code example for an 8-bit microcon-

troller may look like the following:

Chip_Select = 0;

high_byte = spi_read(0x06);

low_byte = spi_read(0x00);

Chip_Select = 1;

delay 0.01ms (stall time)