Register(N)

8-BitDatafor

8-BitDatafor

Register(N+1)

SINGLE-AND MULTIPLE-BYTE TRANSFERS

SINGLE-BYTE WRITE

A6

A5

A4

A3

A2

A1

A0

R/W ACK A7

A6

A5

A4

A3

A2

A1

A0 ACK

D7

D6

D5

D4

D3

D2

D1

D0

ACK

Start

Condition

Stop

Condition

Acknowledge

Acknowledge

Acknowledge

Read/WriteBit

Register

DataByte

TPA2016D2

address and the read/write (R/W) bit to open communication with another device, and then waits for an

acknowledge condition. The TPA2016D2 holds SDA low during the acknowledge clock period to indicate

acknowledgment. When this acknowledgment occurs, the master transmits the next byte of the sequence. Each

device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same

signals via a bidirectional bus using a wired-AND connection.

An external pull-up resistor must be used for the SDA and SCL signals to set the logic high level for the bus.

When the bus level is 5 V, use pull-up resistors between 1 k

Ω and 2 kΩ.

There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last

word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is

shown in Figure 31.

The serial control interface supports both single-byte and multi-byte read/write operations for all registers.

During multiple-byte read operations, the TPA2016D2 responds with data, one byte at a time, starting at the

register assigned, as long as the master device continues to respond with acknowledgments.

data subsequently transmitted, before a stop or start is transmitted, determines the number of registers written.

As Figure 32 shows, a single-byte data write transfer begins with the master device transmitting a start condition

address and the read/write bit, the TPA2016D2 responds with an acknowledge bit. Next, the master transmits the

register byte corresponding to the TPA2016D2 internal memory address being accessed. After receiving the

register byte, the TPA2016D2 again responds with an acknowledge bit. Next, the master device transmits the

data byte to be written to the memory address being accessed. After receiving the register byte, the TPA2016D2

again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the

single-byte data write transfer.

Figure 32. Single-Byte Write Transfer

20

Copyright © 2008, Texas Instruments Incorporated

Product Folder Link(s): TPA2016D2