TPA2016D2RGPR datasheet(19/35 Pages) TI

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TPA2016D2 AGC OPERATION

TPA2016D2 AGC RECOMMENDED SETTINGS

GENERAL I

2C OPERATION

TPA2016D2

www.ti.com ............................................................................................................................................................. SLOS524B – JUNE 2008 – REVISED JUNE 2008

The TPA2016D2 is controlled by the I2C interface. The correct start-up sequence is:

1. Apply the supply voltage to the AVDD and PVDD (L, R)pins.

2. Apply a voltage above VIH to the SDZ pin. The TPA2016D2 powers up the I

2C interface and the control logic.

By default, the device is in active mode (SWS = 0). After a few milliseconds the amplifier will enable the

class-D output stage and become fully operational.

3. The amplifier starts at a gain of 0 dB and the AGC starts ramping the gain after the input signal exceeds the

noise gate threshold.

CAUTION:

Do not interrupt the start-up sequence after changing SDZ from VIL to VIH.

Do not interrupt the start-up sequence after changing SWS from 0 to 1.

The default conditions of TPA2016D2 allows audio playback without I2C control. Refer to Table 4 for entire

default conditions.

There are several options to disable the amplifier:

• Write SPK_EN_R = 0 and SPK_EN_L = 0 to the register (0x01, 6 and 0x01, 7). This write disables each

speaker amplifier, but leaves all other circuits operating.

• Write SWS = 1 to the register (0x01, 5). This action disables most of the amplifier functions.

• Apply V

IL to SDZ. This action shuts down all the circuits and has very low quiescent current consumption.

This action resets the registers to its default values.

CAUTION:

Do not interrupt the shutdown sequence after changing SDZ from VIH to VIL.

Do not interrupt the shutdown sequence after changing SWS from 1 to 0.

Table 2. Recommended AGC Settings for Different Types of Audio Source (VDD = 3.6V)

AUDIO

COMPRESSION

ATTACK TIME

RELEASE TIME

HOLD TIME

FIXED GAIN

LIMITER LEVEL

SOURCE

RATIO

(ms/6 dB)

(ms)

(dB)

(dBV)

Pop Music

4:1

1.28 to 3.84

986 to 1640

137

7.5

Classical

2:1

2.56

1150

137

Jazz

2:1

5.12 to 10.2

3288

—

Rap/ Hip Hop

4:1

1.28 to 3.84

1640

—

7.5

Rock

2:1

3.84

4110

—

Voice/ News

4:1

2.56

1640

—

8.5

The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a

system. The bus transfers data serially one bit at a time. The address and data 8-bit bytes are transferred most

significant bit (MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving device

with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the

bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data

terminal (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on

SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within

the low time of the clock period. Figure 31 shows a typical sequence. The master generates the 7-bit slave

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