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TDA7590 датащи(PDF) 18 Page - STMicroelectronics

номер детали TDA7590
подробное описание детали  Digital signal processing IC for speech and audio applications
PDF  40 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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TDA7590 датащи(HTML) 18 Page - STMicroelectronics

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DSP peripherals
TDA7590
18/40
The key features of the host interface are:
8 bit parallel port "Full-duplex" Dedicated host register bank
Dedicated Mozart Core DSP register core bank.
Register banks map directly into Mozart X memory space
3 transfer modes:
host command
Host to Mozart Core DSP
Mozart Core DSP to host
Access protocols:
Software polled
Interrupt
DMA access by the Mozart Core DSP core
2+ wait states clock cycles per transfer
Supported instructions:
Data transfer between Mozart core and external host using Mozart MOVE
instruction
Simple I/O service routine with bit addressing instructions
IO service using fast interrupts with MOVEP instructions.
7.5
ESSI
The ESSI peripheral enables serial-port communication between the DSP core and external
devices including CODECs, DSP, Microprocessors. The ESSI is capable of driving 12
programmable external pins which can be configured as GPIO ports C and D or ESSI pins.
The key features of the ESSI are:
Independent receiver and transmitter
Synchronous or Asynchronous channel modes Synchronous. Receiver and transmitter
use same clock/sync Asynchronous. Receiver and transmitter may use separate
clock/sync " Up to one transmitter enabled in asynchronous channel mode.
Up to three transmitters enabled in synchronous channel mode.
Normal mode. One word per period.
Network Mode. Up to 32 words per period.
7.6
EOC
The Salieri Extended on-chip memory interface provides access to 40K of on-chip memory.
The Mozart core will treat this memory as if it were external. Access by off-chip expansion
bus masters is permitted. All accesses to the extended on-chip RAM are controlled by the
extended on-chip memory control register. This register determines which combinations of
the Address Attribute pins should be interpreted as accesses to the 40K of RAM.



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