TDA7590 datasheet(8/40 Pages) STMICROELECTRONICS

8 / 40 page

Pin description

TDA7590

8/40

HAD[7]

I/O

Host 8-bit data line 7. Host Data Bus and/or address lines when in

multiplexed mode.

HAD[6]

I/O

Host 8-bit data line 6. Host Data Bus and/or address lines when in

multiplexed mode.

HAD[5]

I/O

Host 8-bit data line 5. Host Data Bus and/or address lines when in

multiplexed mode.

HAD[4]

I/O

Host 8-bit data line 4. Host Data Bus and/or address lines when in

multiplexed mode.

COREVDD

Core Power Supply.

COREVSS

Core Ground.

HAD[3]

I/O

Host 8-bit data line 3. Host Data Bus and/or address lines when in

multiplexed mode.

HAD[2]

I/O

Host 8-bit data line 2. Host Data Bus and/or address lines when in

multiplexed mode.

HAD[1]

I/O

Host 8-bit data line 1. Host Data Bus and/or address lines when in

multiplexed mode.

HAD[0]

I/O

Host 8-bit data line 0. Host Data Bus and/or address lines when in

multiplexed mode.

AA[3]

Address Attributes line 3.Port A address attributes/chip select pins with

programmable polarity.

AA[2]

Address Attributes line 2.Port A address attributes/chip select pins with

programmable polarity.

BR_N

Bus Request. Asserted when Port A requires bus mastership to perform off-

chip accesses.

BB_N

I/O

Bus Busy. Asserted by Port A when bus_busy_in_n is negated and BG_N is

asserted.

IOVDD

IO Power Supply.

IOVSS

IO Ground.

WEN_N

Write Enable.

OEN_N

Output Enable.

AA[1]

Address Attributes line 1.Port A address attributes/chip select pins with

programmable polarity.

AA[0]

Address Attributes line 0.Port A address attributes/chip select pins with

programmable polarity.

BG_N

Bus Grant. When asserted, Port A becomes the bus master elect. Bus

mastership

is attained when bus busy is negated by the current bus master.

AB[0]

Address Bus line 0. Port A external address bus.

AB[1]

Address Bus line 1. Port A external address bus.

IOVDD

IO Power Supply.

Table 1.

Pin function (continued)

N°

Name

Type

Description

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