TDA7590 datasheet(17/40 Pages) STMICROELECTRONICS

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TDA7590

DSP peripherals

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DSP peripherals

7.1

Serial Audio Interface (SAI)

The SAI is used to communicate between the CODEC and the DSPs.

In addition, digital audio can be directly input for processing. There is only one SAI found on

the chip that can be accessed by either the DSP or the DMA controller. The main features of

this block are listed below:

–

Slave Operating Modes, all clock lines can be inputs or outputs

–

Transmit and Receive Interrupt Logic triggers on Left/Right data pairs

–

Receive and Transmit Data Registers have two locations to hold left and right data

7.2

Serial Communication Interface (SCI)

The Serial Communication Interface provides a full duplex port for serial communication to

other DSPs, microprocessors, and peripherals like modems.

The interface supports the following features:

–

No additional logic for connection to other TTL level peripherals

–

Asynchronous bit rates and protocols " High speed synchronous data

transmission.

–

Asynchronous protocol includes Multidrop mode for master/slave operation with

Wakeup on Idle line and Wakeup on Address Bit capability, permitting the SCI to

share a single line with multiple peripherals

–

Transmit and Receive logic can operate asynchronously from each other.

–

A programmable baud-rate generator which provide the transmit and receive

clocks or functions as a general purpose timer.

7.3

I2C Interface

The inter integrated-circuit bus is a simple bi-directional two-wire bus used for efficient inter

IC control. All I2C bus compatible devices incorporate an on-chip interface which allows

them to communicate directly with each other via the I2C bus.

Every component connected to the I2C bus has it s own unique address whether it is a CPU,

memory or some other complex function chip. Each of these chips can act as a receiver

and/or transmitter depending on it s functionality.

7.4

Host Interface (HI)

The host interface is a system-on-chip module that permits connection to the data bus of a

host processor. The HI is capable of driving 16 programmable external pins which can be

configured as an 8 bit parallel port for direct connection to a host processor.

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