28 / 61 page
DM9010
Single Chip Ethernet Controller with General Processor Interface
Preliminary
28
Version: DM9010-DS-P03
Apr. 28, 2005
7:0
TXPLH
PHS0,RW TX Packet Length High byte
7:0
TXPLL
PHS0,RW TX Packet Length Low byte
6.46 Interrupt Status Register (FEH)
Bit
Name
Default
Description
7:6
IOMODE
T0, RO
Bit 7 Bit 6
0
0
16-bit mode
0
1
32-bit mode
1
0
8-bit mode
1
1
Reserved
5
LNKCHG
PHS0,RW/C1
Link Status Change
4
UDRUN
PHS0,RW/C1
Transmit Underrun
3
ROO
PHS0,RW/C1
Receive Overflow Counter Overflow
2
ROS
PHS0,RW/C1
Receive Overflow
1
PT
PHS0,RW/C1
Packet Transmitted
0
PR
PHS0,RW/C1
Packet Received
6.47 Interrupt Mask Register (FFH)
Bit
Name
Default
Description
7
PAR
HPS0,RW
Enable the SRAM read/write pointer to automatically return to the start address
when pointer addresses are over the SRAM size. Driver needs to set. When
driver sets this bit, REG_F5 will set to 0Ch automatically
6
RESERVED
RO
Reserved
5
LNKCHGI
PHS0,RW
Enable Link Status Change Interrupt
4
UDRUNI
PHS0,RW
Enable Transmit Underrun Interrupt
3
ROOI
PHS0,RW
Enable Receive Overflow Counter Overflow Interrupt
2
ROI
PHS0,RW
Enable Receive Overflow Interrupt
1
PTI
PHS0,RW
Enable Packet Transmitted Interrupt
0
PRI
PHS0,RW
Enable Packet Received Interrupt
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
