DM9010
Single Chip Ethernet Controller with General Processor Interface
Preliminary
19
Version: DM9010-DS-P03
Apr. 28, 2005
4
LC
PHS0,RO
Late Collision
It is set when a collision occurs after the collision window of 64 bytes
3
COL
PHS0,RO
Collision packet, collision occurs during transmission
2
EC
PHS0,RO
Excessive Collision
It is set to indicate that the transmission is aborted due to 16 excessive collisions
1:0
RESERVED
0,RO
Reserved
6.6 RX Control Register ( 05H )
Bit
Name
Default
Description
7
HASHALL
PHS0,RW
Filter All address in Hash Table
6
WTDIS
PHS0,RW
Watchdog Timer Disable
When set, the Watchdog Timer (2048 bytes) is disabled. Otherwise it is enabled
5
DIS_LONG
PHS0,RW
Discard Long Packet
Packet length is over 1522byte
4
DIS_CRC
PHS0,RW
Discard CRC Error Packet
3
ALL
PHS0,RW
Pass All Multicast
2
RUNT
PHS0,RW
Pass Runt Packet
1
PRMSC
PHS0,RW
Promiscuous Mode
0
RXEN
PHS0,RW
RX Enable
6.7 RX Status Register ( 06H )
Bit
Name
Default
Description
7
RF
PHS0,RO
Runt Frame
It is set to indicate that the size of the received frame is smaller than 64 bytes
6
MF
PHS0,RO
Multicast Frame
It is set to indicate that the received frame has a multicast address
5
LCS
PHS0,RO
Late Collision Seen
It is set to indicate that a late collision is found during the frame reception
4
RWTO
PHS0,RO
Receive Watchdog Time-Out
It is set to indicate that it receives more than 2048 bytes
3
PLE
PHS0,RO
Physical Layer Error
It is set to indicate that a physical layer error is found during the frame reception
2
AE
PHS0,RO
Alignment Error
It is set to indicate that the received frame ends with a non-byte boundary
1
CE
PHS0,RO
CRC Error
It is set to indicate that the received frame ends with a CRC error
0
FOE
PHS0,RO
FIFO Overflow Error
It is set to indicate that a FIFO overflow error happens during the frame reception
6.8 Receive Overflow Counter Register ( 07H )
Bit
Name
Default
Description
7
RXFU
PHS0,R/C
Receive Overflow Counter Overflow
This bit is set when the ROC has an overflow condition
6:0
ROC
PHS0,R/C
Receive Overflow Counter
This is a statistic counter to indicate the received packet count upon FIFO overflow
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