DM9010
Single Chip Ethernet Controller with General Processor Interface
Preliminary
22
Version: DM9010-DS-P03
Apr. 28, 2005
This bit will not be affected after software reset
3
MAGICEN
P0,RW
When set, it enables Magic Packet Wake up Event
This bit will not be affected after software reset
2
LINKST
P0,RO
When set, it indicates that Link Change and Link Status Change Event occurred
This bit will not be affected after software reset
1
SAMPLEST
P0,RO
When set, it indicates that the sample frame is received and Sample Frame Event
occurred. This bit will not be affected after software reset
0
MAGICST
P0,RO
When set, indicates the Magic Packet is received and Magic packet Event
occurred. This bit will not be affected after a software reset
6.16 Physical Address Register ( 10H~15H )
Bit
Name
Default
Description
7:0
PAB5
E,RW
Physical Address Byte 5 (15H)
7:0
PAB4
E,RW
Physical Address Byte 4 (14H)
7:0
PAB3
E,RW
Physical Address Byte 3 (13H)
7:0
PAB2
E,RW
Physical Address Byte 2 (12H)
7:0
PAB1
E,RW
Physical Address Byte 1 (11H)
7:0
PAB0
E,RW
Physical Address Byte 0 (10H)
6.17 Multicast Address Register ( 16H~1DH )
Bit
Name
Default
Description
7:0
MAB7
X,RW
Multicast Address Byte 7 (1DH)
7:0
MAB6
X,RW
Multicast Address Byte 6 (1CH)
7:0
MAB5
X,RW
Multicast Address Byte 5 (1BH)
7:0
MAB4
X,RW
Multicast Address Byte 4 (1AH)
7:0
MAB3
X,RW
Multicast Address Byte 3 (19H)
7:0
MAB2
X,RW
Multicast Address Byte 2 (18H)
7:0
MAB1
X,RW
Multicast Address Byte 1 (17H)
7:0
MAB0
X,RW
Multicast Address Byte 0 (16H)
6.18 General purpose control Register
( 1EH )
Bit
Name
Default
Description
7
RESERVED
0,RO
Reserved
6:4
GPC64
PH,
111,RO
General Purpose Control 6~4
Define the input/output direction of pins GPIO6~4 respectively.
These bits are all forced to “1”s, so pins GPIO6~4 are output only.
3:1
GPC31
PH,
000,RW
General Purpose Control 3~1
Define the input/output direction of pins GPIO 3~1 respectively.
When a bit is set 1, the direction of correspondent bit of General Purpose Register
is output. Other defaults are input
0
GPC0
PH1,RO
General Purpose Control 0
This bit define the input/output direction of pin GPIO0.
These bits are forced to “1”, so pin GPIO0 is output only.
Pin GPIO0 is forced to output for internal PHYceiver power down function.
6.19 General purpose Register ( 1FH )
Bit
Name
Default
Description
7
RESERVED
0,RO
Reserved
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