DM9010
Single Chip Ethernet Controller with General Processor Interface
Preliminary
27
Version: DM9010-DS-P03
Apr. 28, 2005
6.38 Memory Data Pre-Fetch Read Command without Address Increment Register (F0H)
Bit
Name
Default
Description
7:0
MRCMDX
X,RO
Read data from RX SRAM. After the read of this command, the read pointer of
internal SRAM is unchanged. And the DM9010 starts to pre-fetch the SRAM data
to internal data buffers.
6.39 Memory Data Read Command without Address Increment Register (F1H)
Bit
Name
Default
Description
7:0
MRCMDX1
X,RO
Read data from RX SRAM. After the read of this command, the read pointer of
internal SRAM is unchanged.
6.40 Memory Data Read Command with Address Increment Register (F2H)
Bit
Name
Default
Description
7:0
MRCMD
X,RO
Read data from RX SRAM. After the read of this command, the read pointer is
increased by 1,2, or 4, depends on the operator mode (8-bit,16-bit and 32-bit
respectively)
6.41 Memory Data Read_address Register (F4H~F5H)
Bit
Name
Default
Description
7:0
MDRAH
PHS0,RW Memory Data Read_ address High Byte. It will be set to 0Ch, when IMR bit7 =1
7:0
MDRAL
PHS0,RW Memory Data Read_ address Low Byte
6.42 Memory Data Write Command without Address Increment Register (F6H)
Bit
Name
Default
Description
7:0
MWCMDX
X,WO
Write data to TX SRAM. After the write of this command, the write pointer is
unchanged
6.43 Memory data write command with address increment Register (F8H)
Bit
Name
Default
Description
7:0
MWCMD
X,WO
Write Data to TX SRAM
After the write of this command, the write pointer is increased by 1,2, or 4, depends
on the operator mode. (8-bit, 16-bit,32-bit respectively)
6.44 Memory data write_address Register (FAH~FBH)
Bit
Name
Default
Description
7:0
MDRAH
PHS0,RW Memory Data Write_ address High Byte
7:0
MDRAL
PHS0,RW Memory Data Write_ address Low Byte
6.45 TX Packet Length Register (FCH~FDH)
Bit
Name
Default
Description
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