SBPH400-3 datasheet(26/43 Pages) STMICROELECTRONICS

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SBPH400-3

Power_class

R/W

Power class. Set by software to control the value of the pwr field

transmitted in the self-ID packet. On power reset, this is initialized to

the values of the PC[0:2] pins.

Resume_int

R/W

Resume interrupt enable. When set to 1, the SBPH400 sets

Port_event to 1 if resume operations commence for any port.

Initialized to 0 on power reset.

ISBR

R/W

Initiate short (arbitrated) bus reset. Unless entry to suspend or resume

is in progress for any of the SBPH400’s ports, a write of one to this bit

requests the SBPH400 to arbitrate after a sub-action gap and issue a

short bus reset. Any outstanding fair request is abandoned. Unlike fair

bus requests, the request persists until won, or until a time-out forces

a long bus reset. Always reads as 0.

Loop

R/W

Loop detect interrupt. Set to one when the Tree-ID process detected

a loop. The PHY_interrupt status bit is set when this bit transitions

from 0 to 1. A register write with the value 1 in the field corresponding

to this bit clears the register to zero. A register write with a value 0 to

the field corresponding to this bit is ignored.

Pwr_fail

R/W

Cable power fail interrupt. Set when the PS register changes from 1 to

0. The PHY_interrupt status bit is set when this bit transitions from 0

to 1. A register write with the value 1 in the field corresponding to this

bit clears the register to zero. A register write with a value 0 to the field

corresponding to this bit is ignored.

State t_out

R/W

State time-out interrupt. Set to 1 when the arbitration state machine

has been in any state other than Idle, Tree-ID state T0, Transmit or

Receive for longer than 300

µsec. The PHY_interrupt status bit is set

when this bit transitions from 0 to 1. A register write with the value 1 in

the field corresponding to this bit clears the register to zero. A register

write with a value 0 to the field corresponding to this bit is ignored.

Port_event

R/W

Port event detect. Set to 1 when any of Connected, Bias, Disabled or

Fault change for a port whose Int_enable bit is one, or when resume

operations commence for any port and Resume_int is set to 1. The

PHY_interrupt status bit is set when this bit transitions from 0 to 1. A

clears the register to zero. A register write with a value 0 to the field

corresponding to this bit is ignored.

Enab_accel

R/W

Enable ACK accelerated and fly-by arbitration. Initialized to 0 on

power reset.

Enab_multi

R/W

Enable multi-speed packet concatenation. Initialized to 0 on power-on

reset.

Table 2.16

SBPH400 register fields (continued)

Field

Size

Type

Description

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