SBPH400-3 datasheet(25/43 Pages) STMICROELECTRONICS

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SBPH400-3

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2.8.10 SBPH400 registers

The accessible SBPH400 registers are listed in Table 2.15. The descriptions of the fields are

given in Table 2.16.

Table 2.15

Accessible SBPH400 register

Address

0000

Physical_ID

0001

RHB

IBR

Gap_count

0010

111b (Extended)

rsv

0011b (Total ports)

0011

Max speed

rsv

0000b (Delay)

0100

Link_active

000b (Jitter)

Power_class

0101

Resume_

int

ISBR

Loop

Pwr-fail

State

t_out

Port

event

Enab_

accel

Enab_

multi

0110

rsv

0111

Page_select

rsv

Port_select

1000-1111

Table 2.16

SBPH400 register fields

Field

Size

Type

Description

Physical_ID

The address of the node determined during self-identification.

When set to 1, indicates that the node is the root.

Cable power status. This value always reflects the filtered voltage

sensed on the CPS pin.

RHB

R/W

Root Hold-off bit. When set to 1, instructs the node to attempt to

become the root during the next Tree-ID process. Value on power

reset is 0.

IBR

R/W

Initiate Bus Reset bit. When set to 1, instructs the SBPH400 to initiate

a bus reset for 166

µsec immediately. Always reads as zero.

Gap_Count

R/W

Arbitration timer setting. Used to optimize gap times based on the

topology of the network.

Extended

Always reads as 111b to indicate use of the extended PHY register

map

Total_Ports

Always reads as 3

Max_Speed

010b (maximum speed is S400)

Delay

0000b (maximum repeater delay is 144 ns)

Link_active

R/W

Set or cleared by software. Note that the value of the L bit transmitted

in the self-ID packet is the AND of the Link_active bit and the LPS pin.

Initialized to the value of the LACT configuration pin on power reset.

R/W

Contender. Set or cleared by software to control the value of the C bit

transmitted in the self-ID packet. On power reset this is initialized to

the value of the CMC pin.

Jitter

000b (fastest and slowest repeater delay differ by 20ns)

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