S7G2 datasheet(2/117 Pages) RENESAS

2 / 117 page

R01DS0262EU0150 Rev.1.50

Page 2 of 117

Sep 24, 2025

S7G2 Datasheet

1. Overview

Overview

The MCU integrates multiple series of software- and pin-compatible Arm®-based 32-bit cores that share a common set

of Renesas peripherals to facilitate design scalability and efficient platform-based product development.

The MCU in this series incorporates a high-performance Arm Cortex®-M4 core running up to 240 MHz with the

following features:

 Up to 4-MB code flash memory

 640-KB SRAM

 Graphics LCD Controller (GLCDC)

 2D Drawing Engine (DRW)

 Capacitive Touch Sensing Unit (CTSU)

 Ethernet MAC Controller (ETHERC) with IEEE 1588 PTP, USBFS, USBHS, SD/MMC Host Interface

 Quad Serial Peripheral Interface (QSPI)

 Security and safety features

 Analog peripherals.

1.1

Function Outline

Table 1.1

Arm core

Feature

Functional description

Arm Cortex-M4 core

 Maximum operating frequency: up to 240 MHz

 Arm Cortex-M4 core:

- Revision: r0p1-01rel0

- Armv7E-M architecture profile

- Single precision floating-point unit compliant with the ANSI/IEEE Std 754-2008

 Arm Memory Protection Unit (Arm MPU):

- Armv7 Protected Memory System Architecture

- 8 protect regions

 SysTick timer:

- Driven by SYSTICCLK (LOCO) or ICLK.

Table 1.2

Memory

Feature

Functional description

Code flash memory

Maximum 4 MB of code flash memory. See section 55, Flash Memory in Userʼs Manual.

Data flash memory

64 KB of data flash memory. See section 55, Flash Memory in Userʼs Manual.

Option-setting memory

The option-setting memory determines the state of the MCU after a reset. See section 7,

Option-Setting Memory in Userʼs Manual.

Memory Mirror Function (MMF)

The Memory Mirror Function (MMF) can be configured to mirror the wanted application image

load address in code flash memory to the application image link address in the 23-bit unused

memory space (memory mirror space addresses). Your application code is developed and

linked to run from this MMF destination address. The application code does not need to know

the load location where it is stored in code flash memory. See section 5, Memory Mirror

Function (MMF) in Userʼs Manual.

SRAM

On-chip high-speed SRAM providing either parity-bit or Double-bit Error Detection (DED). The

first 32 KB of SRAM0 is subject to DED. Parity check is performed for other areas. See section

53, SRAM in Userʼs Manual.

Standby SRAM

On-chip SRAM that can retain data in Deep Software Standby mode. See section 54, Standby

SRAM in Userʼs Manual.

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