S7G2 datasheet(4/117 Pages) RENESAS

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R01DS0262EU0150 Rev.1.50

Page 4 of 117

Sep 24, 2025

S7G2 Datasheet

1. Overview

Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a 14-bit down-counter that can be used to reset the MCU when

the counter underflows because the system has run out of control and is unable to refresh the

WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow.

A refresh-permitted period can be set to refresh the counter and used as the condition for

detecting when the system runs out of control. See section 27, Watchdog Timer (WDT) in

Userʼs Manual.

Independent Watchdog Timer (IWDT)

The Independent Watchdog Timer (IWDT) consists of a 14-bit down-counter that must be

serviced periodically to prevent counter underflow. The IWDT provides functionality to reset

the MCU or to generate a non-maskable interrupt or interrupt for a timer underflow. Because

the timer operates with an independent, dedicated clock source, it is particularly useful in

returning the MCU to a known state as a fail safe mechanism when the system runs out of

control. The IWDT can be triggered automatically on a reset, underflow, or refresh error, or by

a refresh of the count value in the registers. See section 28, Independent Watchdog Timer

(IWDT) in Userʼs Manual.

Table 1.4

Event link

Feature

Functional description

Event Link Controller (ELC)

The Event Link Controller (ELC) uses the interrupt requests generated by various peripheral

modules as event signals to connect them to different modules, enabling direct interaction

between the modules without CPU intervention. See section 19, Event Link Controller (ELC)

in Userʼs Manual.

Table 1.5

Direct memory access

Feature

Functional description

Data Transfer Controller (DTC)

A Data Transfer Controller (DTC) module is provided for transferring data when activated by an

interrupt request. See section 18, Data Transfer Controller (DTC) in Userʼs Manual.

DMA Controller (DMAC)

An 8-channel DMA Controller (DMAC) module is provided for transferring data without the

CPU. When a DMA transfer request is generated, the DMAC transfers data stored at the

transfer source address to the transfer destination address. See section 17, DMA Controller

(DMAC) in Userʼs Manual.

Table 1.6

External bus interface

Feature

Functional description

External buses

 CS area (EXBIU): Connected to the external devices (external memory interface)

 SDRAM area (EXBIU): Connected to the SDRAM (external memory interface)

 QSPI area (EXBIUT2): Connected to the QSPI (external device interface).

Table 1.7

Timers (1 of 2)

Feature

Functional description

General PWM Timer (GPT)

The General PWM Timer (GPT) is a 32-bit timer with 14 channels. PWM waveforms can be

generated by controlling the up-counter, down-counter, or up- and down-counter. In addition,

PWM waveforms can be generated for controlling brushless DC motors. The GPT can also be

used as a general-purpose timer. See section 23, General PWM Timer (GPT) in Userʼs

Manual.

Port Output Enable for GPT (POEG)

Use the Port Output Enable for GPT (POEG) function to place the General PWM Timer (GPT)

output pins in the output disable state. See section 22, Port Output Enable for GPT (POEG) in

Userʼs Manual.

Low Power Asynchronous General-

Purpose Timer (AGT)

The Low Power Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used

for pulse output, external pulse width or period measurement, and counting of external events.

This 16-bit timer consists of a reload register and a down-counter. The reload register and the

down-counter are allocated to the same address, and can be accessed with the AGT register.

See section 25, Low Power Asynchronous General-Purpose Timer (AGT) in Userʼs Manual.

Table 1.3

System (2 of 2)

Feature

Functional description

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