S7G2 datasheet(48/117 Pages) RENESAS

48 / 117 page

R01DS0262EU0150 Rev.1.50

Page 48 of 117

Sep 24, 2025

S7G2 Datasheet

2. Electrical Characteristics

Figure 2.9

Power-on reset timing

Figure 2.10

Reset input timing

2.3.4

Wakeup Timing and Duration

Table 2.17

Timing of recovery from low power modes and duration

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

Recovery time

from Software

Standby mode*1

Crystal

resonator

connected

to main

clock

oscillator

System clock source is main

clock oscillator*2

tSBYMC

2.8

Figure 2.11

The division ratio of

all oscillators is 1.

System clock source is PLL

with main clock oscillator*3

tSBYPC

3.2

External

clock input

to main

clock

oscillator

System clock source is main

clock oscillator*4

tSBYEX

280

μs

System clock source is PLL

with main clock oscillator*5

tSBYPE

700

μs

System clock source is sub-clock

oscillator*8

tSBYSC

--1.3

System clock source is LOCO*8

tSBYLO

--1.4

System clock source is HOCO clock

oscillator*6

tSBYHO

300

µs

System clock source is MOCO clock

oscillator*7

tSBYMO

300

µs

Recovery time from Deep Software Standby mode

tDSBY

--1.0

Figure 2.12

Wait time after cancellation of Deep Software Standby mode

tDSBYWT

tcyc

Recovery time

from Software

Standby mode to

Snooze mode

High-speed mode when system clock

source is HOCO (20 MHz)

tSNZ

--68

μs

Figure 2.13

High-speed mode when system clock

source is MOCO (8 MHz)

tSNZ

14*9

μs

Normal mode

duration*10

System clock source is main clock

oscillator

tNML

-*11

--tcycmosc Figure 2.11

System clock source is PLL with main

clock oscillator

VCC

RES

Internal reset signal

(active-low)

tRESWP

tRESWT

RES

Internal reset signal

(active-low)

tRESWD, tRESWS, tRESW

tRESWT

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