S7G2 datasheet(53/117 Pages) RENESAS

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R01DS0262EU0150 Rev.1.50

Page 53 of 117

Sep 24, 2025

S7G2 Datasheet

2. Electrical Characteristics

2.3.6

Bus Timing

Table 2.19

Bus timing

Condition 1: When using the CS area controller (CSC).

BCLK = 8 to 60 MHz

VCC = AVCC0 = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH/VREFH0 = 2.7 V to AVCC0,

VCC_USBHS = AVCC_USBHS = 3.0 to 3.6 V

Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF

EBCLK: High drive output is selected in the port drive capability bit in the PmnPFS register.

Others: Middle drive output is selected in the port drive capability bit in the PmnPFS register.

Condition 2: When using the SDRAM area controller (SDRAMC).

BCLK = SDCLK = 8 to 120 MHz

VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, VREFH/VREFH0 = 3.0 V to AVCC0,

VCC_USBHS = AVCC_USBHS = 3.0 to 3.6 V

Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 15 pF

High drive output is selected in the port drive capability bit in the PmnPFS register.

Condition 3: When using the SDRAM area controller (SDRAMC) and CS area controller (CSC) simultaneously.

BCLK = SDCLK = 8 to 60 MHz

VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, VREFH/VREFH0 = 3.0 V to AVCC0,

VCC_USBHS = AVCC_USBHS = 3.0 to 3.6 V

Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 15 pF

High drive output is selected in the port drive capability bit in the PmnPFS register.

Parameter

Symbol

Min

Max

Unit

Test conditions

Address delay

tAD

12.5

Figure 2.16 to

Figure 2.19

Byte control delay

tBCD

12.5

CS delay

tCSD

12.5

RD delay

tRSD

12.5

Read data setup time

tRDS

12.5

Read data hold time

tRDH

WR/WRn delay

tWRD

12.5

Write data delay

tWDD

12.5

Write data hold time

tWDH

WAIT setup time

tWTS

12.5

Figure 2.20

WAIT hold time

tWTH

Address delay 2 (SDRAM)

tAD2

0.8

6.8

Figure 2.21 to

Figure 2.27

CS delay 2 (SDRAM)

tCSD2

0.8

6.8

DQM delay (SDRAM)

tDQMD

0.8

6.8

CKE delay (SDRAM)

tCKED

0.8

6.8

Read data setup time 2 (SDRAM)

tRDS2

2.9

Read data hold time 2 (SDRAM)

tRDH2

1.5

Write data delay 2 (SDRAM)

tWDD2

6.8

Write data hold time 2 (SDRAM)

tWDH2

0.8

WE delay (SDRAM)

tWED

0.8

6.8

RAS delay (SDRAM)

tRASD

0.8

6.8

CAS delay (SDRAM)

tCASD

0.8

6.8

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