M7020R datasheet(142/150 Pages) STMICROELECTRONICS

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M7020R

142/150

SRAM WRITE with Table(s) of Up to 31 Devices

The following explains the SRAM WRITE opera-

tion done through a table(s) of up to 31 devices

with the following parameters (TLSZ = 10). The di-

agram of such table(s) is shown in Figure 104,

page 143. The following assumes that SRAM ac-

cess is done through M7020R Device 0 – Device

0 is the selected device. Figure 105, page 144 and

Figure 106, page 145 show the timing diagram for

Device 0 and Device 30, respectively.

– Cycle 1A: The host ASIC applies the WRITE In-

struction on CMD[1:0] using CMDV = 1. The DQ

Bus supplies the address with DQ[20:19] set to

'10' to select the SRAM address. The host ASIC

selects the device for which the ID[4:0] matches

the DQ[25:21] lines. The host ASIC also sup-

plies SADR[21:20] on CMD[8:7] in this cycle.

Note: CMD[2] must be set to '0' for SRAM

WRITE because Burst WRITEs into the SRAM

are not supported.

– Cycle 1B: The host ASIC continues to apply the

WRITE Instruction on CMD[1:0] using CMDV =

1. The DQ Bus supplies the address with

DQ[20:19] set to '10' to select the SRAM ad-

dress.

Note: CMD[2] must be set to '0' for SRAM

WRITE because Burst WRITEs into the SRAM

are not supported.

– Cycle 2: The host ASIC continues to drive

DQ[67:0]. The data in this cycle is not used by

the M7020R device.

– Cycle 3: The host ASIC continues to drive

DQ[67:0]. The data in this cycle is not used by

the M7020R device.

At the end of Cycle 3, a new command can begin.

The WRITE is a pipelined operation. The WRITE

Cycle appears at the SRAM Bus, however, with

the same latency as that of a SEARCH Instruction,

as measured from the second cycle of the WRITE

command

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