NXP Semiconductors

PCA9601

Dual bidirectional bus buffer

Refer to Figure 15.

Set master

nominal SCL

VCC1

(V)

+V

cable

(V)

VCC2

(V)

R1

(Ω)

R2

(kΩ)

C2

(pF)

Cable

length

(m)

Cable

capacitance

Cable

delay

HIGH

period

(ns)

LOW

period

(ns)

Effective

bus

clock

speed

(kHz)

Max. slave

response

delay

5

12

5

750 2.2

400 250

n/a (delay

based)

1.25 μs 600

3 850

125

normal

specification

400 kHz parts

5

12

5

750 2.2

220 100

n/a (delay

based)

500 ns

600

2 450

195

normal

specification

400 kHz parts

3.3

5

3.3

330 1

220 25

1 nF

125 ns

260

770

620

meets Fm+

specification

3.3

5

3.3

330 1

100 3

120 pF

15 ns

260

720

690

meets Fm+

specification

Table 7. Examples of bus capability

For more examples of faster alternatives for driving over longer cables such as Cat5

communication cable, see AN10658. Communication at 1 MHz is possible over short

cables and > 400 kHz is possible over 50 m of cable.

10.1 Calculating system delays and bus clock frequency

PCA9601

PCA9601

SCL

SX

local master bus

VCCM

SCL

MASTER

I2C-BUS

Cs

slave bus

capacitance

Cb

buffered bus

wiring capacitance

Cm

master bus

capacitance

Rm

GND (0 V)

VCCB

buffered expansion bus

TX/RX

TX/RX

SX

Rb

Rs

I2C-BUS

SLAVE

VCCS

remote slave bus

002aae880

Effective delay of SCL at slave: 120 + 17VCCM + (2.5 + 4 × 109 × Cb) × VCCB + 10VCCS (ns).

C = F; V = V.

Figure 16. Falling edge of SCL at master is delayed by the buffers and bus fall times

PCA9601

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© NXP B.V. 2022. All rights reserved.

Product data sheet

Rev. 3.1 — 4 January 2022

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