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PCA9601DPZ датащи(PDF) 8 Page - NXP Semiconductors |
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PCA9601DPZ датащи(HTML) 8 Page - NXP Semiconductors |
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8 / 31 page ![]() NXP Semiconductors PCA9601 Dual bidirectional bus buffer Tamb = -40 °C to +85 °C unless otherwise specified; voltages are specified with respect to GND with VCC = 2.5 V to 15 V unless otherwise specified. Typical values are measured at VCC = 5 V and Tamb = 25 °C. Symbol Parameter Conditions Min Typ Max Unit from I2C-bus on SX and SY RX and RY HIGH or LOW; SX and SY LOW ≤ 1 V [1] - -0.3 -1 mA RX and RY HIGH; SX and SY HIGH > 1.4 V [1] - - 10 μA II input current from buffered bus on RX and RY; SX and SY HIGH or LOW; VRX = VRY = 0.4 V [2] - -1.5 -10 μA IL leakage current on buffered bus input on RX and RY; VRX = VRY = 15 V - - 10 μA Output logic LOW level Pins SX and SY on Standard-mode or Fast-mode I2C-bus ISX = ISY = 3 mA; Figure 6 - 0.7 0.74 V ISX = ISY = 0.3 mA; Figure 5 - 0.6 0.65 V on 5 V Fm+ I2C-bus VOL LOW-level output voltage ISX = ISY = 15 mA; Tamb = 0 °C to 85 °C - 0.85 1 V ΔV/ΔT voltage variation with temperature ISX = ISY = 0.3 mA to 3 mA - 0 - %/K Input logic switching threshold voltages Pins SX and SY VIL LOW-level input voltage on normal I2C-bus; Figure 7 [3] - - 425 mV Vth(IH) HIGH-level input threshold voltage on normal I2C-bus; Figure 8 580 - - mV ΔV/ΔT voltage variation with temperature - 0 - %/K Pins RX and RY VIH HIGH-level input voltage fraction of applied VCC 0.55VCC - - V Vth(i) input threshold voltage fraction of applied VCC - 0.48VCC - V VIL LOW-level input voltage fraction of applied VCC - - 0.4VCC V Logic level threshold difference ΔV voltage difference SX and SY; SX output LOW at 0.3 mA to SX input HIGH maximum [4] 50 - - mV Bus release on VCC failure VCC supply voltage SX, SY, TX and TY; voltage at which all buses are to be released at 25 °C - - 1 V Table 6. Characteristics...continued PCA9601 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2022. All rights reserved. Product data sheet Rev. 3.1 — 4 January 2022 8 / 31 |
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