NXP Semiconductors

PCA9601

Dual bidirectional bus buffer

6 Pinning information

6.1 Pinning

PCA9601D

SX

VCC

RX

SY

TX

RY

GND

TY

002aae874

1

2

3

4

6

5

8

7

Figure 2. Pin configuration for SO8

PCA9601DP

SX

VCC

RX

SY

TX

RY

GND

TY

002aae875

1

2

3

4

6

5

8

7

Figure 3. Pin configuration for TSSOP8 (MSOP8)

6.2 Pin description

Symbol

Pin

Description

SX

1

I2C-bus (SDA or SCL)

RX

2

receive signal

TX

3

transmit signal

GND

4

negative supply voltage

TY

5

transmit signal

RY

6

receive signal

SY

7

I2C-bus (SDA or SCL)

VCC

8

positive supply voltage

Table 3. Pin description

7 Functional description

Refer to Figure 1.

The PCA9601 has two identical buffers allowing buffering of SDA and SCL I2C-bus

signals. Each buffer is made up of two logic signal paths, a forward path from the I2C-bus

interface, pins SX and SY which drive the buffered bus, and a reverse signal path from

the buffered bus input, pins RX and RY to drive the I2C-bus interface. These paths:

• sense the voltage state of I2C-bus pins SX (and SY) and transmit this state to pin TX

(and TY respectively), and

• sense the state of pins RX and RY and pull the I2C-bus pin LOW whenever pin RX or

pin RY is LOW.

The rest of this discussion will address only the ‘X’ side of the buffer; the ‘Y’ side is

identical.

7.1 Static level offset card side

The I2C-bus pin SX is specified to allow interfacing with Fast-mode, Fm+ and TTL-based

systems.

PCA9601

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© NXP B.V. 2022. All rights reserved.

Product data sheet

Rev. 3.1 — 4 January 2022

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