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WM8941 датащи(PDF) 77 Page - Wolfson Microelectronics plc |
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WM8941 датащи(HTML) 77 Page - Wolfson Microelectronics plc |
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77 / 96 page ![]() Pre Production WM8941 w PP, Rev 3.3, December 2007 77 REGISTER BITS BY ADDRESS Notes: 1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits). 2. Register bits marked as "Reserved" should not be changed from the default. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 0 (00h) [15:0] RESET / CHIP_ID N/A Writing to this register will apply a software reset. Reading from this register will return the device id Resetting the Chip / Control Interface 15:9 00h Reserved 8 VMID_OP_EN 0 Enables the non-VMID derived bias current generator without enabling the VMID buffer. This bit must be set to 1 if output amplifiers are to be enabled before VMID is active. Once VMID and VMID buffer are enabled this bit can be left set to 0 or left set to 1. Power Management 7 LVLSHIFT_EN 0 Enable bit for the level shifters. 1 for normal operation, 0 for standby. Power Management 6 AUXEN 0 Auxilliary input buffer enable 0 = OFF 1 = ON Auxiliary Inputs 5 PLLEN 0 PLL enable 0=PLL off 1=PLL on Master Clock and Phase Locked Loop (PLL) 4 MICBEN 0 Microphone Bias Enable 0 = OFF (high impedance output) 1 = ON Microphone Biasing Circuit 3 BIASEN 0 Analogue amplifier bias control 0=Disabled 1=Enabled Power Management 2:0 DEVICE_REVI SION 000 Readback from this register will return the device revision in this position Control Interface 2 BUFIOEN 0 Enable bit for the VMID buffer. The VMID buffer is used to maintain a buffered VMID voltage on all analogue input and output pins. 1. for normal operation 0. for standby (where inputs and outputs settle to GND). Enabling the Outputs 1 (01h) 1:0 VMIDSEL 00 Reference string impedance to VMID pin: 00=off (open circuit) 01=50kΩ 10=250kΩ 11=5kΩ Power Management 15:5 000h Reserved 4 BOOSTEN 0 Input BOOST enable 0 = Boost stage OFF 1 = Boost stage ON Input Boost 3 0 Reserved 2 INPPGAEN 0 Input microphone PGA enable 0 = disabled 1 = enabled Input Signal Path 1 0 Reserved 2 (02h) 0 ADCEN 0 ADC Enable Control 0 = ADC disabled 1 = ADC enabled Analogue to Digital Converter (ADC) |
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