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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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WM8941 датащи(PDF) 61 Page - Wolfson Microelectronics plc |
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WM8941 датащи(HTML) 61 Page - Wolfson Microelectronics plc |
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61 / 96 page  Pre Production WM8941 w PP, Rev 3.3, December 2007 61 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 9 LOUTR 0 LOUTR control 0=normal 1=Input mono channel data output on both left and right channels 8 BCP 0 BCLK polarity 0=normal 1=inverted 7 FRAMEP 0 Frame clock polarity (for RJ, LJ and I2S formats) 0=normal 1=inverted DSP Mode control 1 = Configures interface so that MSB is available on 1st BCLK rising edge after FRAME rising edge 0 = Configures interface so that MSB is available on 2nd BCLK rising edge after FRAME rising edge 6:5 WL 10 Word length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits (see note) 4:3 FMT 10 Audio interface Data Format Select: 00=Right Justified 01=Left Justified 10=I2S format 11= DSP/PCM mode 2 DLRSWAP 0 Controls whether DAC data appears in ‘right’ or ‘left’ phases of FRAME clock: 0=DAC data appear in ‘left’ phase of FRAME 1=DAC data appears in ‘right’ phase of FRAME R4 Audio interface control 1 ALRSWAP 0 Controls whether ADC data appears in ‘right’ or ‘left’ phases of FRAME clock: 0=ADC data appear in ‘left’ phase of FRAME 1=ADC data appears in ‘right’ phase of FRAME R5 Companding Control 5 WL8 0 8 Bit Word Length Enable Only recommended for use with companding 0=Word Length controlled by WL 1=8 bits Table 44 Audio Interface Control Note: Right Justified Mode will only operate with a maximum of 24 bits. If 32-bit mode is selected the device will operate in 24-bit mode. |
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