NXP Semiconductors

PCA9537

4-bit I2C-bus and SMBus low power I/O port with interrupt and reset

0 A

S

target address

START condition

R/W acknowledge

from target

aaa-043256

0 0 0 0 0 1 1/0

0

command byte

A

acknowledge

from target

1 2 3 4 5 6 7 8

SCL

9

SDA

DATA 1

A

data to register

acknowledge

from target

data to register

0 0 1 0 0 1

1

P

STOP

condition

Figure 6. Write to configuration or polarity inversion registers

A

S

START condition

R/W

acknowledge

from target

aaa-043257

A

acknowledge

from target

SDA

A

P

acknowledge

from controller

DATA (first byte)

STOP

condition

S

(repeated)

START condition

(cont.)

(cont.)

0 0 1 0 0 1 1 A

1

R/W

acknowledge

from target

target address

at this moment controller-transmitter becomes controller-receiver

and target-receiver becomes target-transmitter

NA

no acknowledge

from controller

COMMAND BYTE

0 0 1 0 0 1

1

0

data from register

DATA (last byte)

data from register

target address

Figure 7. Read from register

0 0 1 0 0 1 1 A

S 1

target address

START condition

R/W acknowledge

from target

aaa-043258

data from port

A

acknowledge

from controller

SDA

1

no acknowledge

from controller

read from

port

data into

port

data from port

DATA 1

DATA 4

INT

DATA 4

DATA 2

DATA 3

P

STOP

condition

tv(INT)

trst(INT)

th(D)

tsu(D)

1 2 3 4 5 6 7 8

SCL

9

DATA 1

This figure assumes the command byte has previously been programmed with 00h.

Transfer of data can be stopped at any moment by a STOP condition.

Expanded diagram is shown in Figure 15.

Figure 8. Read input port register

PCA9537

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2021. All rights reserved.

Product data sheet

Rev. 7 — 8 September 2021

COMPANY PUBLIC

8 / 25