NXP Semiconductors

PCA9537

4-bit I2C-bus and SMBus low power I/O port with interrupt and reset

6.3 Power-on reset

When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9537

in a reset condition until VDD has reached VPOR. At that point, the reset condition is

released and the PCA9537 registers and state machine will initialize to their default

states. Thereafter, VDD must be lowered below 0.2 V to reset the device.

For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the

operating voltage.

6.4 RESET input

A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The

PCA9537 registers and SMBus/I2C-bus state machine will be held in their default state

until the RESET input is once again HIGH. This input requires a pull-up resistor to VDD if

no active connection is used.

6.5 Interrupt output

The open-drain interrupt output (INT) is activated when one of the port pins changes

state and the pin is configured as an input. The interrupt is de-activated when the input

returns to its previous state or the Input Port register is read.

Note that changing an I/O from an output to an input may cause a false interrupt to occur

if the state of the pin does not match the contents of the Input Port register.

6.6 I/O port

When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-

impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V.

If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on

the state of the Output Port register. Care should be exercised if an external voltage is

applied to an I/O configured as an output because of the low-impedance paths that exist

between the pin and either VDD or VSS.

PCA9537

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2021. All rights reserved.

Product data sheet

Rev. 7 — 8 September 2021

COMPANY PUBLIC

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