ADIS16354SLASHPCBZ datasheet(19/28 Pages) AD

19 / 28 page

ADIS16354

Rev. 0 | Page 19 of 28

–20

–40

–60

–80

–100

–120

–140

0.001

0.01

0.1

FREQUENCY (

f/fS)

N = 2

N = 4

N = 16

N = 64

Figure 30. Bartlett Window FIR Frequency Response

Dynamic Range

The ADIS16354 provides three dynamic range settings: ±75°/s,

±150°/s, and ±300°/s. The lower dynamic range settings (75, 150)

limit the minimum filter tap sizes in order to maintain the resolu-

tion as the measurement range decreases. The recommended

order for programming the SENS/AVG register is upper byte

(sensitivity), followed by lower byte (filtering). The contents of

the SENS/AVG register are nonvolatile.

Table 21. SENS/AVG Register Definition

Address

Default

Format

Access

0x39, 0x38

0x0402

N/A

R/W

Table 22. SENS/AVG Bit Descriptions

Bits

Value

Description

[15:11]

Not used

[10:8]

Measurement range (sensitivity) selection

100

300°/s (default condition)

010

150°/s, filter taps ≥ 4 (Bits [2:0] ≥ 0x02)

001

75°/s, filter taps ≥ 16 (Bits [2:0] ≥ 0x04)

[7:3]

Not used

[2:0]

Filter tap setting, number of taps, N = 2M,

for example, 011, N = 23 = 8 taps

Auxiliary DAC

The auxiliary DAC provides a 12-bit level adjustment function.

The AUX_DAC register controls the operation of this feature. It

offers a rail-to-rail buffered output that has a range of 0 V to 2.5 V.

The DAC can drive its output to within 5 mV of the ground

reference when it is not sinking current. As the output

approaches ground, the linearity begins to degrade (100 LSB

beginning point). As the sink current increases, the nonlinear

range increases. The DAC output latch function, contained in

the COMMAND register, provides continuous operation while

writing each byte of this register. The contents of this register

are volatile, which means that the desired output level must be

set after every reset and power cycle event.

Table 23. AUX_DAC Register Definition

Address

Default

Format

Access

0x31, 0x30

0x0000

Binary

R/W

Table 24. AUX_DAC Bit Descriptions

Bits

Description

[15:12]

Not used

[11:0]

Data bits

0x0000 = 0 V output, 0x0FFF = 2.5 V output

See the COMMAND register for use of the DAC latch

command, which enables the DAC to update its output based

on the value in the AUX-DAC register.

General-Purpose Input/Output

The ADIS16354 provides two general-purpose pins that enable

digital input/output control using the SPI. The GPIO_CTRL

control register establishes the configuration of these pins and

handles the SPI-to-pin controls. Each pin provides the flexibil-

ity of both input (read) and output (write) operations.

For example, writing 0x0202 to this register establishes Line 2 as

an output and sets its level as a 1. Writing 0x0000 to this register

establishes both lines as inputs, and their status can be read through

Bit 8 and Bit 9 of this register.

The digital input/output lines are also available for data-ready and

alarm/error indications. In the event of conflict, the following

priority structure governs the digital input/output configuration:

MSC_CTRL

ALM_CTRL

GPIO_CTRL

Table 25. GPIO_CTRL Register Definition

Address

Default

Format

Access

0x33, 0x32

0x0000

N/A

R/W

Table 26. GPIO_CTRL Bit Descriptions

Bits

Description

[15:10]

Not used

[9]

General-purpose input/output Line 2 data level

1 = high, 0 = low

[8]

General-purpose input/output Line 1 data level

1 = high, 0 = low

[7:2]

Not used

[1]

General-purpose input/output Line 2, data direction

control

1 = output, 0 = input

[0]

General-purpose input/output Line 1, data direction

control

1 = output, 0 = input

The contents of the GPIO_CTRL register are volatile.

ADIS16354/PCBZ датащи(PDF) 19 Page - Analog Devices

ADIS16354/PCBZ датащи(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

датащи скачать

ссылки URL