ADIS16354SLASHPCBZ datasheet(18/28 Pages) AD

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ADIS16354

Rev. 0 | Page 18 of 28

Table 15. COMMAND Register Definition

Address

Default

Format

Access

0x3F, 0x3E

N/A

Write only

Table 16. COMMAND Bit Descriptions

Bits

Description

[15:8]

Not used

[7]

Software reset command

[6:5]

Not used

[4]

Precision autonull command

[3]

Flash update command

[2]

Auxiliary DAC data latch

[1]

Factory calibration restore command

[0]

Autonull command

OPERATIONAL CONTROL

Internal Sample Rate

The internal sample rate defines how often data output variables

are updated, independent of the rate at which they are read out

on the SPI port. The SMPL_PRD register controls the ADIS16354

internal sample rate and has two parts: a time base and a multi-

plier. The sample period can be calculated using the following

equation:

TS = TB × (NS + 1)

where:

TS is the sample period.

TB is the time base.

NS is the multiplier.

The default value is the minimum register setting, 0x01, which

corresponds to the maximum sample rate of 819.2 samples per

second. The contents of this register are nonvolatile.

Table 17. SMPL_PRD Register Definition

Address

Default

Format

Access

0x37, 0x36

0x0001

N/A

R/W

Table 18. SMPL_PRD Bit Descriptions

Bits

Description

[15:8]

Not used

[7]

Time base, 0 = 0.61035 ms, 1 = 18.921 ms

[6:0]

Multiplier (add 1 before multiplying by the time base)

An example calculation of the sample period for the device is

If SMPL_PRD = 0x0007, Bits [7:0] = 00000111

Bit 7 = 0, so TB = 0.61035 ms

Bits [6:0] = 0000111 = 7 = NS

TS = TB × (NS + 1) = = 0.61035 ms × (7 + 1) = 4.8828 ms

fS = 1∕TS = 204.8 SPS

The sample rate setting has a direct impact on the SPI data rate

capability. For SMPL_PRD settings ≤ 0x09 (fast mode), the SPI

SCLK can run at a rate up to 2.0 MHz. For SMPL_PRD settings

> 0x09 (normal mode), the SPI SCLK can run at a rate up to

300 kHz.

The sample rate setting also affects the power dissipation.

The normal mode power dissipation is approximately 67% less

than the fast mode power dissipation. The two different modes

of operation offer a system-level trade-off between performance

(sample rate, serial transfer rate) and power dissipation.

Power Management

The ADIS16354 offers two different shutdown options:

programmable shutdown period and indefinite shutdown.

Raising Bit 8 activates the indefinite shutdown period. Writing

the appropriate sleep time to the lower byte of the SLP_CNT

following example illustrates this relationship:

Bits [7:0] = 00000110 = 6 codes = 3 seconds

At the completion of the programmed duration, the ADIS16354

returns to normal operation. If measurements are required

before sleep period completion or if it is necessary to end the

indefinite shutdown, the ADIS16354 can be awakened by pull-

ing the CS line down to a 0 state, then returning it to a 1 state.

Otherwise, the CS line must be kept in a 1 state to maintain sleep

mode.

When writing a sleep time to the SLP_CNT register, the CS

signal must be raised to a 1 before the command takes effect.

Power cycle recovery will be a normal startup, because the

contents of SLP_CNT are volatile.

Table 19. SLP_CNT Register Definition

Address

Scale1

Default

Format

Access

0x3B, 0x3A

0.5 sec

0x0000

Binary

R/W

1 Scale is the weight of each LSB in the lower byte of this register.

Table 20. SLP_CNT Bit Descriptions

Bits

Description

[15:9]

Not used

[8]

Indefinite shutdown control bit

[7:0]

Data bits, 0.5 sec/LSB

Digital Filtering

Each sensor’s signal conditioning circuit has an analog bandwidth

of approximately 350 Hz. The ADIS16354 provides a Bartlett

Window FIR filter for additional noise reduction on all of the

output data registers. The SENS/AVG register controls the

number of taps in power-of-two step sizes, from zero to six

Filter setup requires one simple step: write the appropriate M

factor to the assigned bits in the SENS/AVG register. The bit

assignments are listed in Table 22. The frequency response

relationship for this filter is:

(

)

()

sin

)

(

)

(

)

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