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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TUSB1046AI-DCI датащи(PDF) 9 Page - Texas Instruments |
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TUSB1046AI-DCI датащи(HTML) 9 Page - Texas Instruments |
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9 / 48 page  9 TUSB1046A-DCI www.ti.com SLLSF13B – JUNE 2017 – REVISED MAY 2019 Product Folder Links: TUSB1046A-DCI Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated 6.9 Timing Requirements MIN NOM MAX UNIT USB Gen 1 tIDLEEntry Delay from U0 to electrical idle See Figure 14 10 ns tIDELExit_U1 U1 exist time: break in electrical idle to the transmission of LFPS See Figure 14 6 ns tIDLEExit_U2U3 U2/U3 exit time: break in electrical idle to transmission of LFPS 10 µs tRXDET_INTVL RX detect interval while in Disconnect 12 ms tIDLEExit_DISC Disconnect Exit Time 10 µs tExit_SHTDN Shutdown Exit Time 1 ms tDIFF_DLY Differential Propagation Delay See Figure 13 300 ps tR, tF Output Rise/Fall time (see Figure 15) 20%-80% of differential voltage measured 1.7 inch from the output pin 35 ps tRF_MM Output Rise/Fall time mismatch 20%-80% of differential voltage measured 1.7 inch from the output pin 2.6 ps 6.10 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AUXp or AUXn and SBU1 or SBU2 tAUX_PD Switch propagation delay 400 ps tAUX_SW_OFF Switching time CTL1 to switch OFF. Not including TCTL1_DEBOUNCE. 500 ns tAUX_SW_ON Switching time CTL1 to switch ON 500 ns tAUX_INTRA Intra-pair output skew 100 ps USB3.1 and DisplayPort mode transition requirement GPIO mode tGP_USB_4DP Min overlap of CTL0 and CTL1 when transitioning from USB 3.1 only mode to 4-Lane DisplayPort mode or vice versa. 4 µs CTL1 and HPDIN tCTL1_DEBOUNCE CTL1 and HPDIN debounce time when transitioning from H to L. 2 10 ms I2C (Refer to Figure 11) fSCL I2C clock frequency 1 MHz tBUF Bus free time between START and STOP conditions 0.5 µs tHDSTA Hold time after repeated START condition. After this period, the first clock pulse is generated 0.26 µs tLOW Low period of the I2C clock 0.5 µs tHIGH High period of the I2C clock 0.26 µs tSUSTA Setup time for a repeated START condition 0.26 µs tHDDAT Data hold time 0 μs tSUDAT Data setup time 50 ns tR Rise time of both SDA and SCL signals 120 ns tF Fall time of both SDA and SCL signals 20 × (V(I2C)/5.5 V) 120 ns tSUSTO Setup time for STOP condition 0.26 μs Cb Capacitive load for each bus line 150 pF |
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