TUSB1046AI-DCI datasheet(8/48 Pages) TI2

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TUSB1046A-DCI

SLLSF13B – JUNE 2017 – REVISED MAY 2019

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AC Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

C(P1dB-HF)

High frequency 1-dB compression

point

at 5 GHz, 200 mVPP < VID

< 2000 mVPP

1000

mVPP

fLF

Low frequency cutoff

200 mVPP< VID < 2000 mVPP

kHz

TX output deterministic jitter

200 mVPP < VID < 2000 mVPP, PRBS7,

10 Gbps

0.11

UIpp

200 mVPP < VID < 2000 mVPP, PRBS7,

8.1 Gbps

0.08

UIpp

TX output total jitter

200 mVPP < VID < 2000 mVPP, PRBS7,

10 Gbps

0.15

UIpp

200 mVPP < VID < 2000 mVPP, PRBS7,

8.1 Gbps

0.135

UIpp

DisplayPort Receiver (DP[3:0]p or DP[3:0]n)

VID(PP)

Peak-to-peak input differential dynamic voltage range

2000

VIC

Input common mode voltage

C(AC)

AC coupling capacitance

200

EQ(DP)

Receiver equalization

DPEQ[1:0] at 4.05 GHz

Data rate

HBR3

8.1

Gbps

R(ti)

Input termination resistance

100

120

DisplayPort Transmitter (TX1p or TX1n, TX2p or TX2n, RX1p or RX1n, RX2p or RX2n)

ITX(SHORT)

TX short circuit current

TX± shorted to GND

VTX(DC-CM)

Common-mode voltage bias in the transmitter (DC)

1.75

AUXp or AUXn and SBU1 or SBU2

RON

Output ON resistance

VCC = 3.3V; VI = 0 to 0.4 V for AUXp;

VI = 2.7 V to 3.6 V for AUXn

ΔRON

ON resistance mismatch within pair

VCC = 3.3 V; VI = 0 to 0.4 V for AUXP;

VI = 2.7 V to 3.6 V for AUXN

2.5

RON(FLAT)

ON resistance flatness (RON max –

RON min) measured at identical VCC

and temperature

VCC = 3.3 V; VI = 0 to 0.4 V for AUXp;

VI = 2.7 V to 3.6 V for AUXn

V(AUXP_DC_CM)

AUX Channel DC common mode

voltage for AUXp and SBU1.

VCC = 3.3 V

0.4

V(AUXN_DC_CM)

AUX Channel DC common mode

voltage for AUXn and SBU2

VCC = 3.3 V

2.7

3.6

C(AUX_ON)

ON-state capacitance

VCC = 3.3 V; CTL1 = 1; VI = 0 V

or 3.3 V

C(AUX_OFF)

OFF-state capacitance

VCC = 3.3 V; CTL1 = 0; VI = 0 V

or 3.3 V

6.8 DCI Specific Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DCI_CLK and DCI_DAT LVCMOS Outputs

VOL

Low-Level output voltage

VCC = 3 V; IOL = 2 mA; CL = 10 pF

0.45

VOH

High-Level output voltage

VCC = 3 V; IOL = –2 mA;

2.4

RDCI

Output characteristic impedance

tPERIOD

DCI Clock period

Measured at 50%

6.67

tVALID

Rising edge of DCI clock to DCI

data valid

tDCI_RISE

DCI output rise time

Measured at 20% to 80%.

350

tDCI_FALL

DCI output fall time

Measured at 80% to 20%

350

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