LP38788, LP38788-ADJ

www.ti.com

SNVS802B – APRIL 2012 – REVISED OCTOBER 2012

The output capacitor must be located not more than 0.5" from the output pin and returned to a clean analog

ground to the LP38788 GND pin.

CHARGE PUMP

The charge pump is running when both the input voltage is above the UVLO threshold (2.65V typical) and the EN

pin voltage is above the VEN(ON) threshold (1.25V typical). The typical charge pump operating frequency is 3.5

MHz.

A low leakage 10 nF (0.01

μF) to 100 nF (0.1 μF) storage capacitor is required between the CP pin and ground

to store the energy required for gate drive of the internal NMOS pass device.

Do not make any other connection to the CP pin. Loading this pin in any manner will degrade regulator

performance. No external biasing may be applied to, or derived from, this pin, as permanent damage to the

internal charge pump circuitry may occur.

SETTING THE OUTPUT VOLTAGE

Current sourced from the SET pin, through R1 and R2, must be kept to less than 100 µA. The minimum allowed

value for R2 is 12.9 k

Ω

ISET = VFB / R2

(1)

R2MIN = VFB(MAX) / 100 μA

(2)

R2MIN = 12.9 kΩ

(3)

The values for R1 and R2 may be adjusted as needed to achieve the desired output voltage as long as the value

for R2 is no less than 12.9 k

Ω. The maximum recommended value for R2 is 100 kΩ.

The following equation is used to determine the output voltage:

VOUT = ( VFB x ( 1 + ( R1 / R2 ) ) ) + VOS

(4)

Alternately, the following formula can be used to determine the appropriate R1 value for a given R2 value:

R1 = R2 x ( ( (VOUT - VOS) / VFB) - 1)

(5)

The following table suggests some ±1% values for R1 and R2 for a range of output voltages using the typical VFB

value of 1.200V. This is not a definitive list, as other combinations exist that will provide similar, possibly better,

performance.

Target VOUT

R1

R2

Typical VOUT

4.70V

47.5 k

Ω

16.2 k

Ω

4.719V

5.00V

47.5 k

Ω

15.0 k

Ω

5.000V

ENABLE INPUT OPERATION

The Enable pin (EN) is pulled high internally by a 2

μA (typical) current source from the IN pin, and clamped at

4.9V (typical) by a zener. Pulling the EN pin low will turn the output off.

LLP THERMAL CONSIDERATIONS

The value of

θJ−A for the LLP package is specifically dependent on PCB copper area, copper thickness, the

number of layers, and thermal vias under the exposed thermal pad (DAP). Please refer to AN-1520 (Literature

Number: SNVA183A) for general guidelines for mounting packages with exposed thermal pads.

Exceeding the maximum allowable power dissipation defined by the final

θJ−A will cause excessive die

temperature, and the regulator may go into thermal shutdown.

Note that Thermal Shutdown is provided as a safety feature and is outside the guaranteed Operating Ratings

temperature range. Operation with a junction temperature (TJ) above 125°C is not recommended as device

behavior is not guaranteed.

Copyright © 2012, Texas Instruments Incorporated

Submit Documentation Feedback

9

Product Folder Links: LP38788 LP38788-ADJ