IN

EN

CP

GND(CP)

OUT

SET

FB

GND

OUT

OUT(FB)

IN

IN(CP)

Exposed Pad

on Bottom

(DAP)

1

2

3

4

5

6

7

8

9

10

11

12

LP38788, LP38788-ADJ

SNVS802B – APRIL 2012 – REVISED OCTOBER 2012

www.ti.com

Connection Diagram

Connect LLP DAP to GND

Figure 1. LP38788SD-ADJ (Top View)

12-Lead LLP Package

Pin Functions

Pin Descriptions

Pin

Name

Function

1, 2

IN

Device unregulated input voltage pins. Connect pins together at the package.

3

IN(CP)

Charge pump input voltage pin. Connect directly to pins 1 and 2 at the package.

Charge pump output. See CHARGE PUMP section in the Applications Information for

4

CP

more information.

Enable pin. A Logic high level is required on this pin to enable the LDO output. A Logic

low level will turn the output off and reduce the operating current of the device. See

5

EN

ENABLE INPUT OPERATION section in the Applications Information for more

information.

6

GND

Device charge pump ground pin.

7

GND

Device analog ground pin.

8

FB

Feedback pin for programming the output voltage.

Internally filtered pre-buffered output. A feedback resistor divider network from this pin

9

SET

to FB and GND will set the output voltage of the device.

10

OUT(FB)

OUT buffer feedback pin. Connect directly to pins 11 and 12 at the package.

11, 12

OUT

Device regulated output voltage pins. Connect pins together at the package.

The exposed die attach pad on the bottom of the package should be connected to a

Exposed Pad

DAP

thermal pad at ground potential. See LLP THERMAL CONSIDERATIONS section in

the Applications Information for more information.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

2

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Product Folder Links: LP38788 LP38788-ADJ