EN

GND(CP)

CP

IN(CP)

OUT(FB)

SET

FB

GND

UVLO

Charge Pump

3.5 MHz

Current

Limit

Thermal

Shutdown

VREF

1.200V

IEN

2 PA

6V

LP38788-ADJ

OUT

OUT

IN

IN

Active Ripple

Rejection

200 mV

PMOS

ISET

40 PA

200 mV

LP38788, LP38788-ADJ

SNVS802B – APRIL 2012 – REVISED OCTOBER 2012

www.ti.com

Block Diagram

Application Information

PACKAGE INFORMATION

The LP38788SD-ADJ is available in the 12-Lead LLP (SDA12B) surface mount package that allows for

increased power dissipation compared to the standard PSOP-8 and LLP-8 packages.

EXTERNAL CAPACITORS

Like any low-dropout regulator, the LP38788SD-ADJ requires external capacitors for regulator stability. These

capacitors must be correctly selected for optimum performance.

INPUT CAPACITOR: Minimum recommended input capacitance is 1 µF.

Capacitor tolerance and variations due temperature and applied voltage must be considered when selecting a

capacitor to assure the minimum requirement of input capacitance is met over the intended operating range.

The input capacitor must be located as close as physically possible to the input pin and returned to a clean

analog ground. Any good quality Tantalum capacitor may be used, while a Ceramic capacitor should be X5R or

X7R rated with appropriate adjustments due to the loss of capacitance value from the applied DC voltage.

OUTPUT CAPACITOR: The LP38788 requires an output capacitor whose value is at least 1 µF, however a

minimum output capacitance of 10 µF is strongly recommended. While the LP38788 is designed to work with

Ceramic output capacitors, the output capacitor can be Ceramic, Tantalum, or a combination. Capacitance type,

tolerance, ESR, as well as temperature and voltage characteristics, must be considered when selecting an

output capacitor for the application.

8

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Product Folder Links: LP38788 LP38788-ADJ